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SN100KT5574NT

更新时间： 2024-10-15 19:16:15
品牌 Logo 应用领域
德州仪器 - TI 光电二极管接口集成电路锁存器
页数 文件大小 规格书
8页 71K
描述
Octal ECL-to-TTL Translator With D-type Edge-Triggered Flip-Flops And 3-State OU 24-PDIP 0 to 70

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SN100KT5574NT 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：DIP
包装说明：DIP, DIP24,.3针数：24
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.84
最大延迟：7.4 ns输入特性：STANDARD
接口集成电路类型：ECL TO TTL TRANSLATORJESD-30 代码：R-PDIP-T24
长度：31.64 mm标称负供电电压：-4.5 V
位数：1功能数量：8
端子数量：24最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
输出锁存器或寄存器：REGISTER输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP24,.3封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5,-4.5 V认证状态：Not Qualified
座面最大高度：5.08 mm子类别：Level Translators
最大压摆率：110 mA最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：NO技术：BIPOLAR
温度等级：COMMERCIAL端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.62 mm
Base Number Matches：1

SN100KT5574NT 数据手册

 浏览型号SN100KT5574NT的Datasheet PDF文件第2页浏览型号SN100KT5574NT的Datasheet PDF文件第3页浏览型号SN100KT5574NT的Datasheet PDF文件第4页浏览型号SN100KT5574NT的Datasheet PDF文件第5页浏览型号SN100KT5574NT的Datasheet PDF文件第6页浏览型号SN100KT5574NT的Datasheet PDF文件第7页 
SN100KT5574  
OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE  
EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS  
SDZS009 – D3418, JANUARY 1990  
DW OR NT PACKAGE  
(TOP VIEW)  
• 100K Compatible  
• ECL Clock and TTL Control Inputs  
• Flow-Through Architecture Optimizes PCB  
1Q  
2Q  
3Q  
4Q  
1D  
2D  
3D  
4D  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
Layout  
2
• Center Pin V , V , and GND  
3
CC EE  
Configurations Minimize High-Speed  
Switching Noise  
4
V
OE(TTL)  
5
CC  
GND  
V
• Package Options Include “Small Outline”  
6
EE  
GND  
GND  
5Q  
6Q  
7Q  
GND  
CLK(ECL)  
5D  
6D  
7D  
Packages and Standard Plastic DIPs  
7
8
description  
9
10  
11  
12  
This octal ECL-to-TTL translator is designed to  
provide efficient translation between a 100K ECL  
signal environment and a TTL signal environment.  
8Q  
8D  
This device is designed specifically to improve the performance and density of ECL-to-TTL CPU/bus-oriented  
functions such as memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.  
The eight flip-flops of the SN100KT5574 are edge-triggered D-type flip-flops. On the positive transition of the  
clock, the Q outputs are set to the logic levels that were set up at the D inputs.  
A buffered output-enable input (OE) can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance third state and increased drive provide the capability to drive  
bus lines without need for interface or pullup components.  
The output-enable input OE does not affect the internal operations of the flip-flops. Old data can be retained  
or new data can be entered while the outputs are off.  
The SN100KT5574 is characterized for operation from 0°C to 85°C.  
FUNCTION TABLE  
OUTPUT  
INPUTS  
(TTL)  
OE  
L
CLK  
D
L
Q
L
↑
↑
L
H
X
X
H
Q
L
L
X
o
H
Z
PRODUCTION DATA information is current as of publication date. Products  
conform to specifications per the terms of Texas Instruments standard  
warranty. Production processing does not necessarily include testing of all  
parameters.  
Copyright 1990, Texas Instruments Incorporated  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1
12345678

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