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SN100KT5574DWR

更新时间： 2024-10-15 13:13:43
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德州仪器 - TI 触发器输出元件
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7页 70K
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SN100KT5574DWR 数据手册

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SDZS009 − D3418, JANUARY 1990  
DW OR NT PACKAGE  
(TOP VIEW)  
• 100K Compatible  
• ECL Clock and TTL Control Inputs  
• Flow-Through Architecture Optimizes PCB  
1Q  
2Q  
3Q  
4Q  
1D  
2D  
3D  
4D  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
Layout  
2
• Center Pin V , V , and GND  
3
CC EE  
Configurations Minimize High-Speed  
Switching Noise  
4
V
OE(TTL)  
5
CC  
GND  
V
• Package Options Include “Small Outline”  
6
EE  
GND  
GND  
5Q  
GND  
CLK(ECL)  
5D  
Packages and Standard Plastic DIPs  
7
8
description  
9
6Q  
7Q  
8Q  
6D  
7D  
8D  
10  
11  
12  
This octal ECL-to-TTL translator is designed to  
provide efficient translation between a 100K ECL  
signal environment and a TTL signal environment.  
This device is designed specifically to improve the performance and density of ECL-to-TTL CPU/bus-oriented  
functions such as memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.  
The eight flip-flops of the SN100KT5574 are edge-triggered D-type flip-flops. On the positive transition of the  
clock, the Q outputs are set to the logic levels that were set up at the D inputs.  
A buffered output-enable input (OE) can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance third state and increased drive provide the capability to drive  
bus lines without need for interface or pullup components.  
The output-enable input OE does not affect the internal operations of the flip-flops. Old data can be retained  
or new data can be entered while the outputs are off.  
The SN100KT5574 is characterized for operation from 0°C to 85°C.  
FUNCTION TABLE  
OUTPUT  
INPUTS  
(TTL)  
OE  
L
CLK  
↑
D
L
Q
L
L
↑
H
X
X
H
Q
L
L
o
H
X
Z
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Copyright 1990, Texas Instruments Incorporated  
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ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ  
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1
1234567

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与SN100KT5574DWR相关器件

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SN100KT5574NT TI

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 		Octal ECL-to-TTL Translator With D-type Edge-Triggered Flip-Flops And 3-State OU 24-PDIP 0
SN100KT5576NT TI

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 		OCTAL ECL TO TTL TRANSLATOR, INVERTED OUTPUT, PDIP24
SN100KT5578 TI

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 		OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE
SN100KT5578DW TI

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 		Octal TTL-to-ECL Translator With D-type Edge-Triggered Flip-Flops And Output ENA 24-SOIC 0
SN100KT5578NT TI

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 		Octal TTL-to-ECL Translator With D-type Edge-Triggered Flip-Flops And Output ENA 24-PDIP 0
SN100M0010A5F51012 YAGEO

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 		Aluminum Electrolytic Capacitor, Non-polarized, Aluminum (wet), 100V, 20% +Tol, 20% -Tol,
SN100M0010APF-0811 YAGEO

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 		Aluminum Electrolytic Capacitor, Non-polarized, Aluminum (wet), 100V, 20% +Tol, 20% -Tol,
SN100M0010B3F50811 YAGEO

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 		Aluminum Electrolytic Capacitor, Non-polarized, Aluminum (wet), 100V, 20% +Tol, 20% -Tol,
SN100M0010L5SW1012 YAGEO

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 		Aluminum Electrolytic Capacitor, Non-polarized, Aluminum, 100V, 20% +Tol, 20% -Tol, 10uF,
SN100M0022A3FV.M1320 YAGEO

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 		Aluminum Electrolytic Capacitor, Non-polarized, Aluminum (wet), 100V, 20% +Tol, 20% -Tol,

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