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SMJ320C50AGFA40 PDF预览

SMJ320C50AGFA40

更新时间： 2024-11-13 20:52:35
品牌 Logo 应用领域
德州仪器 - TI 时钟外围集成电路
页数 文件大小 规格书
37页 959K
描述
16-BIT, 40MHz, OTHER DSP, CPGA141, CERAMIC, PGA-141

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SMJ320C50AGFA40 技术参数

生命周期：Obsolete零件包装代码：PGA
包装说明：IPGA,针数：141
Reach Compliance Code：unknownECCN代码：3A001.A.2.C
HTS代码：8542.31.00.01风险等级：5.6
地址总线宽度：16桶式移位器：NO
边界扫描：YES最大时钟频率：40 MHz
外部数据总线宽度：16格式：FIXED POINT
内部总线架构：MULTIPLEJESD-30 代码：S-CPGA-P141
长度：26.93 mm低功率模式：NO
端子数量：141最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：IPGA封装形状：SQUARE
封装形式：GRID ARRAY, INTERSTITIAL PITCH认证状态：Not Qualified
座面最大高度：5.2 mm最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子形式：PIN/PEG
端子节距：2.54 mm端子位置：PERPENDICULAR
宽度：26.93 mmuPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：1

SMJ320C50AGFA40 数据手册

 浏览型号SMJ320C50AGFA40的Datasheet PDF文件第2页浏览型号SMJ320C50AGFA40的Datasheet PDF文件第3页浏览型号SMJ320C50AGFA40的Datasheet PDF文件第4页浏览型号SMJ320C50AGFA40的Datasheet PDF文件第5页浏览型号SMJ320C50AGFA40的Datasheet PDF文件第6页浏览型号SMJ320C50AGFA40的Datasheet PDF文件第7页 
SMJ320C50/SMQ320C50  
DIGITAL SIGNAL PROCESSOR  
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001  
HFG PACKAGE  
(TOP VIEW)  
D Military Operating Temperature Range:  
-- 5 5 °C to 125°C  
D Processed to MIL-PRF-38535  
D Fast Instruction Cycle Time (30 ns and  
40 ns)  
1
99  
67  
D Source-Code Compatible With All C1x  
and C2x Devices  
D RAM-Based Operation  
-- 9 K × 16-Bit Single-Cycle On-Chip  
Program/Data RAM  
-- 1056 × 16-Bit Dual-Access On-Chip  
Data RAM  
33  
D 2K × 16-Bit On-Chip Boot ROM  
D 224K × 16-Bit Maximum Addressable  
External Memory Space (64K Program,  
64K Data, 64K I/O, and 32K Global)  
GFA PACKAGE  
(TOP VIEW)  
D 32-Bit Arithmetic Logic Unit (ALU)  
-- 32-bit Accumulator (ACC)  
A
C
B
-- 32-Bit Accumulator Buffer (ACCB)  
D
F
E
G
J
D 16-Bit Parallel Logic Unit (PLU)  
D 16 × 16-Bit Multiplier, 32-Bit Product  
D 11 Context-Switch Registers  
H
K
L
M
P
T
D Two Buffers for Circular Addressing  
D Full-Duplex Synchronous Serial Port  
D Time-Division Multiplexed Serial Port (TDM)  
D Timer With Control and Counter Registers  
N
R
U
W
V
2
4
6
8 10 12 14 16 18  
7 9 11 13 15 17 19  
1
3
5
D 16 Software Programmable Wait-State  
Generators  
PQ PACKAGE  
(TOP VIEW)  
D Divide-by-One Clock Option  
D IEEE 1149.1† Boundary Scan Logic  
D Operations Are Fully Static  
1 132  
117  
17  
18  
116  
D Enhanced Performance Implanted CMOS  
(EPIC™) Technology Fabricated by Texas  
Instruments  
D Packaging  
-- 141-Pin Ceramic Grid Array (GFA Suffix)  
-- 132-Lead Ceramic Quad Flat Package  
(HFG Suffix)  
-- 132-Lead Plastic Quad Flat Package  
(PQ Suffix)  
84  
50  
51  
83  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture  
EPIC is a trademark of Texas Instruments Incorporated.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
Copyright © 1998, Texas Instruments Incorporated  
On products compliant to MIL-STD-883, Class B, all parameters are  
tested unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443  
1234567...37

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