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SLG47105 PDF预览

SLG47105

更新时间: 2024-11-06 14:57:39
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
253页 3748K
描述
HVPAK? Programmable Mixed-Signal Matrix with Four Outputs with Operating Voltage up to 13.2 V and up to 2 A Current per Output

SLG47105 数据手册

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ꢀꢀꢀꢀ  
SLG47105  
GreenPAK Programmable Mixed-Signal Matrix with High  
Voltage Features  
General Description  
The SLG47105 provides a small, low power component for commonly used Mixed-Signal and Bridge functions. The user  
creates their circuit design by programming the one time programmable (OTP) Non-Volatile Memory (NVM) to configure the  
interconnect logic, the IO Pins, the High Voltage Pins, and the macrocells of the SLG47105.  
Configurable PWM macrocells in combination with Special High Voltage outputs will be useful for a motor drive or load drive  
applications. High Voltage pins allow to design smart level translators or to drive the high voltage high current load.  
Key Features  
Two Power Supply Inputs:  
One Voltage Reference (Vref) Output  
Five Multi-Function Macrocells  
Four Selectable DFF/LATCH/3-bit LUTs + 8-bit Delay/  
Counters  
One Selectable DFF/LATCH/4-bit LUT + 16-bit Delay/  
Counter  
Twelve Combination Function Macrocells  
Three Selectable DFF/LATCH or 2-bit LUTs  
One Selectable Programmable Pattern Generator or  
2-bit LUT  
2.5 V (±8 %) to 5.0 V (±10 %) VDD  
3.3 V (±9 %) to 12.0 V (±10 %) VDD2  
Four High Voltage High Current Drive GPOs  
Dual/Single Full Bridge Driver Option  
Quad/Dual/Single Half Bridge Driver Option  
Slew Rate Modes:  
Motor Driver Mode  
Pre-Driver (MOSFET Driver) Mode  
SLEEP Function  
Low RDS ON High Side + Low Side resistance = 0.4  
2 A Peak, 1.5 A RMS per Full Bridge (at VDD2 = 5 V,  
T = 25 °C) (Note 1)  
4 A Peak, 3 A RMS per two Full Bridge connected in  
parallel (at VDD2 = 5 V, T = 25 °C) (Note 1)  
2 A Peak, 1.5 A RMS per Half Bridge GPO  
(at VDD2 = 5 V, T = 25 °C) (Note 1)  
Integrated Protections:  
Six Selectable DFF/LATCH or 3-bit LUTs  
One Selectable Pipe Delay or Ripple Counter or 3-bit  
LUT  
One Selectable DFF/LATСH or 4-bit LUT  
Two PWM Macrocells  
Flexible 8-bit/7-bit PWM Mode with the Duty Cycle  
Control  
16 Preset Duty Cycle Registers Switching Mode for  
PWM Sine or Other Waveforms (Note 2)  
Serial Communications  
Over Current Protection (OCP)  
Short Circuit Protection  
Under-Voltage Lockout (UVLO)  
Thermal Shutdown (TSD)  
I2C Protocol Interface  
Programmable Delay with Edge Detector Output  
Additional Logic Function – One Deglitch Filter with Edge  
Detectors  
SENSE_A, SENSE_B Inputs that are connected to the  
Current Comparators for Current Control  
Fault Signal Indicator individual per Full Bridge:  
OCP  
Two Oscillators (OSC)  
2.048 kHz Oscillator  
25 MHz Oscillator  
Analog Temperature Sensor with ACMP Connected Out-  
put  
POR  
One Time Programmable Memory  
Operating Temperature Range: -40 °C to 85 °C  
RoHS Compliant/Halogen-Free  
20-pin STQFN: 2 mm x 3 mm x 0.55 mm, 0.4 mm pitch  
UVLO  
TSD  
Differential Amplifier with Integrator and Comparator for  
Motor Speed Control Function  
Two Current Sense Comparators with Dynamical Vref  
Mode  
Two High-Speed General Purpose ACMPs  
Modes: UVLO, OCP, TSD, Voltage Monitor, Current  
Monitor  
Applications  
Smart Locks  
Toys  
Personal Computers and Servers  
Consumer Electronics  
Motor Drivers  
HV MOSFET Drivers  
Video Security Cameras  
LED Matrix Dimmers  
Note 1 Power dissipation and thermal limits must be observed. See Section 3.3  
Note 2 For all PWM features see Section 13.  
Datasheet  
4-Jul-2023  
Revision 3.10  
1 of 252  
© 2023 Renesas Electronics Corporation  
CFR0011-120-00  

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