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SK4414T PDF预览

SK4414T

更新时间: 2024-09-17 19:12:59
品牌 Logo 应用领域
商升特 - SEMTECH 驱动接口集成电路驱动器
页数 文件大小 规格书
4页 77K
描述
Line Transceiver, 4 Func, 4 Driver, 4 Rcvr, PQFP32, TQFP-32

SK4414T 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:TFQFP,针数:32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
差分输出:YES驱动器位数:4
输入特性:DIFFERENTIAL接口集成电路类型:LINE TRANSCEIVER
接口标准:GENERAL PURPOSEJESD-30 代码:S-PQFP-G32
JESD-609代码:e3长度:5 mm
功能数量:4端子数量:32
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:TFQFP
封装形状:SQUARE封装形式:FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
最大接收延迟:0.55 ns接收器位数:4
座面最大高度:1.2 mm最大供电电压:5.5 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED最大传输延迟:0.55 ns
宽度:5 mmBase Number Matches:1

SK4414T 数据手册

 浏览型号SK4414T的Datasheet PDF文件第2页浏览型号SK4414T的Datasheet PDF文件第3页浏览型号SK4414T的Datasheet PDF文件第4页 
AN1004  
Interfacing Between LVDS and ECL /  
LVECL / PECL / LVPECL  
HIGH-PERFORMANCE PRODUCTS  
Interfacing LVDS with PECL and LVPECL  
About LVDS  
Signal level translation between PECL / LVPECL to  
LVDS can be achieved using resistor divider network;  
however, when using discrete logic the signal volt-  
age level would shift with respect to supply voltage  
and ambient temperature fluctuation. In turn, this  
will diminish the signal integrity and cause duty cycle  
distortion. To avoid such problems, Semtech has  
designed a fully integrated IC devices that translate  
PECL / LVPECL signal into LVDS and LVDS to PECL /  
LVPECL type signals. Refer to table 1 for a list of  
these devices. Semtech also offers a fully integrated  
receiver / driver device with true LVDS inputs and  
outputs (SK1303) in an 8-lead SOIC and MSOP pack-  
ages.  
As the bandwidth increases in Telecom / Datacom  
and even in consumer / commercial applications ,  
the high speed, low power, noise, and cost of LVDS  
signal broaden the scope of its application beyond  
the traditional technologies such as ECL / PECL.  
LVDS (Low Voltage Differential Signaling) are differ-  
ential signals with typical 350 mV swing and a DC  
offset of 1.2V. When moving signals from box-to-  
box or board-to-board (i.e. flat panel display). LVDS  
is the right solution because it generates less noise,  
consumes less power and it is very cost effective.  
Figure 1 shows different voltage levels for different  
types of signals.  
LVDS signals can easily be terminated with a 100 W  
resistor across the differential LVDS outputs. Most  
devices with LVDS I / O provide the 100W resistor  
internally at its inputs to minimize component count  
(i.e. SK1301). Figure 2 is an example of LVDS out-  
put termination. For PECL / LVPECL output termina-  
tion refer to application note AN1003.  
PECL  
LVPECL  
+
LVDS  
HSTL  
0V  
V
CC  
NC  
D
8
1
ECL /LVECL  
-
Figure 1: Relative differences among various I/O standards  
Q
2
7
100  
LVDS  
D*  
R
3
6
Q*  
T
Note:  
HSTL (High-Speed Transceiver Logic) signals are used in computing de-  
sign applications such as memory drivers and high-speed CPU-to-Memory  
interfacing.  
R
T
VEE  
NC  
5
SK1301  
4
V
TT  
Figure 2: LVDS Termination  
Revision 1/December 20, 2001  
www.semtech.com  
1

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