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SI5018

更新时间： 2024-11-25 03:32:07

品牌	Logo	应用领域
芯科 - SILICON		时钟
页数	文件大小	规格书
22页	213K
描述
SiPHY⑩ OC-48/STM-16 CLOCK AND DATA RECOVERY IC WITH FEC

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SI5018 数据手册

Si5018

SiPHY™ OC-48/STM-16 CLOCK AND DATA RECOVERY IC WITH FEC

Features

Complete high-speed, low-power, CDR solution includes the following:

! Supports OC-48 /STM-16 & FEC! Exceeds all SONET/SDH jitter

specifications

! Low power—270 mW

(typ OC-48)

! Jitter generation

3.0 mUI

(typ)

! Small footprint: 4x4 mm

rms

! Device powerdown

! Loss-of-lock indicator

! Single 2.5 V Supply

! DSPLL™ Eliminates external

Ordering Information:

loop filter components

! 3.3 V tolerant control inputs

See page 17.

Applications

Pin Assignments

Si5018

! SONET/SDH/ATM routers

! Add/drop multiplexers

! Optical transceiver modules

! SONET/SDH regenerators

! Board level serial links

! Digital cross connects

! SONET/SDH test equipment

description

20 19 18 17 16

REXT

VDD

The Si5018 is a fully-integrated low-power clock and data recovery (CDR)

IC designed for high-speed serial communication systems. It extracts

timing information and data from a serial input at OC-48/STM-16 data

rates. In addition, support for 2.7 Gbps data streams is also provided for

applications that employ forward error correction (FEC). DSPLL™

technology eliminates sensitive noise entry points thus making the PLL

less susceptible to board-level interaction and helping to ensure optimal

jitter performance.

PWRDN/CAL

VDD

GND

Pad

Connection

GND

DOUT+

DOUT–

VDD

REFCLK+

REFCLK–

The Si5018 represents a new standard in low jitter, low power, and small

size for high speed CDRs. It operates from a single 2.5 V supply over the

industrial temperature range (–40 to 85 °C).

Functional Block Diagram

LOL

DSPLL^TM

Phase-Locked

Loop

DIN +

DIN –

DOUT +

DOUT –

BUF

Retim er

PW RDN/CAL

CLKOUT +

CLKOUT –

Bias

REXT

REFCLKIN +

REFCLKIN –

Rev. 1.2 1/04

Si5018-DS12

12 3 4 5 6 7...22

中文翻译

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