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SI3442CDV-T1-GE3 PDF预览

SI3442CDV-T1-GE3

更新时间: 2024-02-09 14:22:53
品牌 Logo 应用领域
威世 - VISHAY 开关光电二极管晶体管
页数 文件大小 规格书
11页 223K
描述
TRANSISTOR SMALL SIGNAL, FET, FET General Purpose Small Signal

SI3442CDV-T1-GE3 技术参数

生命周期:Obsolete包装说明:SMALL OUTLINE, R-PDSO-G6
Reach Compliance Code:unknownECCN代码:EAR99
风险等级:7.67配置:SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压:20 V最大漏极电流 (Abs) (ID):8 A
最大漏极电流 (ID):6.6 A最大漏源导通电阻:0.027 Ω
FET 技术:METAL-OXIDE SEMICONDUCTORJEDEC-95代码:MO-193AA
JESD-30 代码:R-PDSO-G6元件数量:1
端子数量:6工作模式:ENHANCEMENT MODE
最高工作温度:150 °C封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED极性/信道类型:N-CHANNEL
最大功率耗散 (Abs):2.7 W子类别:FET General Purpose Power
表面贴装:YES端子形式:GULL WING
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
晶体管应用:SWITCHING晶体管元件材料:SILICON
Base Number Matches:1

SI3442CDV-T1-GE3 数据手册

 浏览型号SI3442CDV-T1-GE3的Datasheet PDF文件第5页浏览型号SI3442CDV-T1-GE3的Datasheet PDF文件第6页浏览型号SI3442CDV-T1-GE3的Datasheet PDF文件第7页浏览型号SI3442CDV-T1-GE3的Datasheet PDF文件第9页浏览型号SI3442CDV-T1-GE3的Datasheet PDF文件第10页浏览型号SI3442CDV-T1-GE3的Datasheet PDF文件第11页 
AN823  
Vishay Siliconix  
Mounting LITTLE FOOTR TSOP-6 Power MOSFETs  
Surface mounted power MOSFET packaging has been based on  
integrated circuit and small signal packages. Those packages  
have been modified to provide the improvements in heat transfer  
required by power MOSFETs. Leadframe materials and design,  
molding compounds, and die attach materials have been  
changed. What has remained the same is the footprint of the  
packages.  
Since surface mounted packages are small, and reflow soldering  
is the most common form of soldering for surface mount  
components, “thermal” connections from the planar copper to the  
pads have not been used. Even if additional planar copper area is  
used, there should be no problems in the soldering process. The  
actual solder connections are defined by the solder mask  
openings. By combining the basic footprint with the copper plane  
on the drain pins, the solder mask generation occurs automatically.  
The basis of the pad design for surface mounted power MOSFET  
is the basic footprint for the package. For the TSOP-6 package  
outline drawing see http://www.vishay.com/doc?71200 and see  
http://www.vishay.com/doc?72610 for the minimum pad footprint.  
In converting the footprint to the pad set for a power MOSFET, you  
must remember that not only do you want to make electrical  
connection to the package, but you must made thermal connection  
and provide a means to draw heat from the package, and move it  
away from the package.  
A final item to keep in mind is the width of the power traces. The  
absolute minimum power trace width must be determined by the  
amount of current it has to carry. For thermal reasons, this  
minimum width should be at least 0.020 inches. The use of wide  
traces connected to the drain plane provides a low impedance  
path for heat to move away from the device.  
REFLOW SOLDERING  
In the case of the TSOP-6 package, the electrical connections are  
very simple. Pins 1, 2, 5, and 6 are the drain of the MOSFET and  
are connected together. For a small signal device or integrated  
circuit, typical connections would be made with traces that are  
0.020 inches wide. Since the drain pins serve the additional  
function of providing the thermal connection to the package, this  
level of connection is inadequate. The total cross section of the  
copper may be adequate to carry the current required for the  
application, but it presents a large thermal impedance. Also, heat  
spreads in a circular fashion from the heat source. In this case the  
drain pins are the heat sources when looking at heat spread on the  
PC board.  
Vishay Siliconix surface-mount packages meet solder reflow  
reliability requirements. Devices are subjected to solder reflow as a  
test preconditioning and are then reliability-tested using  
temperature cycle, bias humidity, HAST, or pressure pot. The  
solder reflow temperature profile used, and the temperatures and  
time duration, are shown in Figures 2 and 3.  
Figure 1 shows the copper spreading recommended footprint for  
the TSOP-6 package. This pattern shows the starting point for  
utilizing the board area available for the heat spreading copper. To  
create this pattern, a plane of copper overlays the basic pattern on  
pins 1,2,5, and 6. The copper plane connects the drain pins  
electrically, but more importantly provides planar copper to draw  
heat from the drain leads and start the process of spreading the  
heat so it can be dissipated into the ambient air. Notice that the  
planar copper is shaped like a “T” to move heat away from the  
drain leads in all directions. This pattern uses all the available area  
underneath the body for this purpose.  
0.167  
4.25  
Ramp-Up Rate  
+6_C/Second Maximum  
120 Seconds Maximum  
70 180 Seconds  
240 +5/0_C  
0.074  
1.875  
Temperature @ 155 " 15_C  
Temperature Above 180_C  
Maximum Temperature  
Time at Maximum Temperature  
Ramp-Down Rate  
0.014  
0.35  
0.122  
3.1  
0.026  
0.65  
20 40 Seconds  
+6_C/Second Maximum  
0.049  
1.25  
0.049  
1.25  
0.010  
0.25  
FIGURE 2. Solder Reflow Temperature Profile  
FIGURE 1. Recommended Copper Spreading Footprint  
Document Number: 71743  
27-Feb-04  
www.vishay.com  
1

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