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SG-710PTKFREQC PDF预览

SG-710PTKFREQC

更新时间: 2024-10-30 09:57:47
品牌 Logo 应用领域
精工 - SEIKO /
页数 文件大小 规格书
3页 46K
描述
TTL Output Clock Oscillator, 1.8MHz Min, 50MHz Max

SG-710PTKFREQC 数据手册

 浏览型号SG-710PTKFREQC的Datasheet PDF文件第2页浏览型号SG-710PTKFREQC的Datasheet PDF文件第3页 
Crystal oscillator  
HIGH-FREQUENCY CRYSTAL OSCILLATOR  
SG-710 series  
Products number  
Q3371 0xxxx xxx 00  
• Ceramic package with 1.5 mm thickness.  
• Excellent environmental capability.  
• Low current consumption due to use of C-MOS technology.  
• Low current consumption by output enable function (OE) or standby function  
(ST).  
Actual size  
Specifications (characteristics)  
SG-710PTK  
SG-710PHK  
SG-710ECK  
Remarks  
Symbol  
f0  
Item  
Specifications  
1.8000 MHz to  
80.0000 MHz  
1.8000 MHz to  
67.0000 MHz  
1.8000 MHz to  
50.0000 MHz  
Output frequency range  
VDD-GND  
VDD  
Max. supply voltage  
-0.5 V to +7.0 V  
±0.5 V  
-55 °C to +125 °C  
Power source  
voltage  
Operating voltage  
Storage temperature  
Operating temperature  
5.0  
V
3.3 V ±0.3 V  
TSTG  
Stored as bare product after unpacking  
Please contact us on availability of -40 °C to +85 °C  
B,C:-10 °C to +70 °C, M:-40 °C to +85 C°  
Temperature  
range  
-10 °C to +70 °C (-40 °C to +85 °C  
)
TOPR  
-6  
-6  
-6  
f/f0  
B: ±50 x 10 C: ± 100 x 10 M: ± 100 x 10  
Frequency stability  
Iop  
IOE  
IST  
No load condition  
OE=GND(PTK, PHK)  
ST=GND(ECK)  
24 mA Max.  
12 mA Max.  
40 mA Max.  
16 mA Max.  
18 mA Max.  
Current consumption  
Output disable current  
Standby current  
10 µA Max.  
40 % to 60 %  
45 % to 55 %  
40 % to 60 %  
C-MOS load: 1/2 VDD level  
TTL load: 1.4 V level  
OH=-16 mA(PTK,PHK),-2 mA(ECK)  
tw/ t  
Duty  
45 % to 55 %  
2.4 V Min.  
0.4 V Max.  
10 TTL Max.  
(15 pF Max.)  
2.0 V Min.  
0.8 V Max.  
VOH  
VOL  
N
I
High output voltage  
Low output voltage  
Output load  
condition (fan out)  
V
DD -0.5 V Min.  
0.5 V Max.  
10 TTL Max.  
50 pF Max.  
2.0 V Min.  
0.8 V Max.  
5 ns Max.  
0.9  
0.1  
x
x
V
DD Min.  
I
OL= 16 mA(PTK,PHK), 2 mA(ECK)  
VDD Max.  
TTL  
C-MOS  
CL  
15 pF Max.  
0.7 x VDD Min.  
0.3 x VDD Max.  
6 ns Max.  
VIH  
VIL  
OE terminal(PTK,PHK)  
_
Output enable/disable input voltage  
ST terminal(ECK)  
C-MOS load: 10 %90  
TTL load: 0.4 V 2.4 V  
C-MOS load: 90 %10  
TTL load: 2.4 V 0.4 V  
%
VDD  
C-MOS level  
TTL level  
tTLH  
tTHL  
Output rise time  
5 ns Max.  
5 ns Max.  
%
VDD  
5 ns Max.  
6 ns Max.  
C-MOS level  
Output fall time  
TTL level  
Oscillation start up time  
Aging  
10 ms Max.  
tOSC  
Time at minimum operating voltage to be 0 s  
-6  
±5 x 10 /year Max.  
Ta= +25 °C, VDD = 5.0 V/3.3 V(ECK)  
fa  
Three drops on a hard board from 750 mm  
2
or excitation test with 29400 m/s x 0.3 ms x  
1/2sine wave in 3 directions  
-6  
±10 x 10 Max.  
S.R.  
Shock resistance  
(Unit: mm)  
(Unit: mm)  
Recommended soldering pattern  
External dimensions  
# 4  
# 3  
#3  
#4  
5.08  
1.8  
Pin terminal  
NO.  
1
OE or ST  
E
40.000  
HC724A  
2
GND  
OUT  
VDD  
3
4
#2  
# 1  
# 2  
#1  
L
1.4  
L
W
7.5 Max. 5.0 Max.  
7.2 Max. 5.2 Max.  
SG -710  
SG -710  
K
W
5.08  
5.08  
39  

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