Crystal oscillator
HIGH-FREQUENCY CRYSTAL OSCILLATOR
SG-710 series
Product number (please refer to page 1)
Q3371 0xxxx xxx 00
• Ceramic package with 1.5 mm thickness.
• Excellent environmental capability.
• Low current consumption due to use of C-MOS technology.
• Low current consumption by output enable function (OE) or standby function
(ST).
Actual size
Specifications
Item
Symbol
f0
Remarks
SG-710PTK
SG-710PHK
SG-710ECK
1.8000 MHz to
50.0000 MHz
1.8000 MHz to
80.0000 MHz
-0.5 V to +7.0 V
1.8000 MHz to
67.0000 MHz
Output frequency range
Refer to page 31. "Frequency range"
Max. supply voltage
Power source
voltage
Temperature
range
VDD-GND
VDD
TSTG
Operating voltage
Storage temperature
Operating temperature
5.0 V ±0.5 V
-55 °C to +125 °C
-10 °C to +70 °C (-40 °C to +85 °C)
B: ±50 x 10-6 C: ± 100 x 10-6 M: ± 100 x 10-6
3.3 V ±0.3 V
Stored as bare product after unpacking
Refer to page 31. "Frequency range"
TOPR
B,C:-10 °C to +70 °C, M:-40 °C to +85 °C
Frequency stability
∆f/f0
Fo ≤ 25 MHz, No load condition (ECK: Fo ≤ 32 MHz, No load condition)
Fo ≤ 50 MHz, No load condition
13 mA Max.
24 mA Max.
15 mA Max.
26 mA Max.
34 mA Max.
40 mA Max.
5 mA Max.
10 mA Max.
13 mA Max.
16 mA Max.
8 mA Max.
15 mA Max.
18 mA Max.
—
Iop
Current consumption
Fo ≤ 67 MHz, No load condition
—
—
Fo ≤ 80 MHz, No load condition
Fo ≤ 25 MHz, OE=GND(PTK, PHK)
Fo ≤ 50 MHz, OE=GND(PTK, PHK)
Fo ≤ 67 MHz, OE=GND(PTK, PHK)
Fo ≤ 80 MHz, OE=GND(PTK, PHK)
ST=GND(ECK)
CMOS load: 1/2 VDD level
TTL load: 1.4 V level
IOH=-16 mA(PTK,PHK),-2 mA(ECK)
6 mA Max.
12 mA Max.
—
—
—
—
—
IOE
Output disable current
—
Standby current
Duty
IST
—
10 µA Max.
40 % to 60 %
—
0.9 x VDD Min.
0.1 x VDD Max.
—
15 pF Max.
0.7 x VDD Min.
0.3 x VDD Max.
6 ns Max.
—
45 % to 55 %
40 % to 60 %
VDD -0.5 V Min.
0.5 V Max.
10 TTL Max.
50 pF Max.
2.0 V Min.
tw/ t
45 % to 55 %
2.4 V Min.
0.4 V Max.
10 TTL Max.
(15 pF Max.)
2.0 V Min.
0.8 V Max.
—
High output voltage
Low output voltage
Output load
VOH
VOL
N
CL
VIH
VIL
IOL= 16 mA(PTK,PHK), 2 mA(ECK)
TTL
CMOS
condition (fan out)
OE terminal(PTK,PHK)
ST terminal(ECK)
Output enable/disable input voltage
Output rise time
0.8 V Max.
5 ns Max.
CMOS load: 10 %→90 % VDD
TTL load: 0.4 V→2.4 V
CMOS load: 90 %→10 % VDD
TTL load: 2.4 V→0.4 V
tTLH
tTHL
5 ns Max.
—
5 ns Max.
—
—
5 ns Max.
6 ns Max.
Output fall time
Oscillation start up time
Aging
tOSC
10 ms Max.
±5 x 10-6/year Max.
Time at minimum operating voltage to be 0 s
fa
Ta= +25 °C, VDD = 5.0 V/3.3 V, First year
Three drops on a hard board from 750 mm
or excitation test with 29400 m/s2 x 0.3 ms x
1/2sine wave in 3 directions
±10 x 10-6 Max.
Shock resistance
S.R.
(Unit: mm)
(Unit: mm)
H
5.08
#4
# 4
# 3
#3
L
W
7.3 ±0.2 4.8 ±0.2 1.3 ±0.1
SG -710
SG -710
K
1.8
+0.1
7.0 ±0.2 5.0 ±0.2 1.4
W
-0.15
#2
# 1
# 2
#1
Pin terminal
OE or ST
GND
NO.
1
L
1.4
Note.
OE Pin (PTK, PHK, PTW, PHW, PCW)
2
3
OUT
OE pin - "H" or "open" : Specified frequency output.
OE pin - "L" : Output is high impedance.
4
VDD
ST pin (STW, SHW, SCW)
ST pin - "H" or "open" : Specified frequency output.
5.08
5.08
ST pin - "L" : Output is low level (weak pull-down), oscillation stops.
ST pin (ECK)
ST pin - "H" or "open" : Specified frequency output.
37
ST pin - "L" : Output is high impedance., oscillation stops.