Datasheet > SDA2526-5

SDA2526-5

更新时间： 2024-10-26 22:17:15

品牌	Logo	应用领域
英飞凌 - INFINEON		存储可编程只读存储器
页数	文件大小	规格书
12页	277K
描述
Nonvolatile Memory 2-Kbit E2PROM with I2C Bus

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中文翻译

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技术参数
数据手册

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SDA2526-5 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	DIP	包装说明：	PLASTIC, DIP-8
针数：	8	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.32.00.51
风险等级：	5.6	最大时钟频率 (fCLK)：	0.1 MHz
数据保留时间-最小值：	10	耐久性：	100000 Write/Erase Cycles
I2C控制字节：	1010DDDR	JESD-30 代码：	R-PDIP-T8
JESD-609代码：	e0	长度：	10 mm
内存密度：	2048 bit	内存集成电路类型：	EEPROM
内存宽度：	8	功能数量：	1
端子数量：	8	字数：	256 words
字数代码：	256	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	256X8	封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装等效代码：	DIP8,.3
封装形状：	RECTANGULAR	封装形式：	IN-LINE
并行/串行：	SERIAL	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V	认证状态：	Not Qualified
座面最大高度：	4.2 mm	串行总线类型：	I2C
最大待机电流：	0.02 A	子类别：	EEPROMs
最大压摆率：	0.02 mA	最大供电电压 (Vsup)：	5.25 V
最小供电电压 (Vsup)：	4.75 V	标称供电电压 (Vsup)：	5 V
表面贴装：	NO	技术：	MOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.62 mm	Base Number Matches：	1

SDA2526-5 数据手册

Nonvolatile Memory 2-Kbit E²PROM

with I²C Bus

SDA 2526-5

Preliminary Data

MOS IC

Features

● Word-organized programmable nonvolatile memory in

n-channel floating-gate technology (E PROM)

● 256 × 8-bit organization

● Supply voltage 5 V

● Serial 2-line bus for data input and output (I C Bus)

● Reprogramming mode, 10 ms erase/write cycle

● Reprogramming by means of on-chip control (without

external control)

P-DIP-8-1

● Check for end of programming process

● Data retention > 10 years

● More than 10 reprogramming cycles per address

● Compatible with SDA 2526. Exceptions: Conditions for

total erase and current consumption I_CC

Type

Ordering Code

Package

SDA 2526-5

Q67100-H5095

P-DIP-8-1

Circuit Description

I C Bus Interface

The I C Bus is a bidirectional 2-line bus for the transfer of data between various integrated circuits.

It consists of a serial data line SDA and a serial clock line SCL. The data line requires an external

pull-up resistor to V_CC(open drain output stage).

The possible operational states of the I C Bus are shown in figure 1. In the quiescent state, both

lines SDA and SCL are high, i.e. the output stage of the data line is disabled. As long a SCL remains

"1", information changes on the data bus indicate the start or the end of data transfer between two

components.

The transition on SDA from "1" to "0" is a start condition, the transition from "0" to "1" is a stop

condition. During a data transfer the information on the data bus will only change while the clock line

SCL is "0". The information on SDA is valid as long as SCL is "1".

In conjunction with an I C Bus system, the memory component can operate as a receiver and as a

transmitter (slave receiver or slave transmitter). Between a start and stop condition, information is

always transmitted in byte-organized form. Between the falling edge of the eighth clock pulse and

a ninth acknowledge clock pulse, the memory component sets the SDA-line to low as a confirmation

of reception, if the chip select conditions have been met. During the output of data, the data output

of the memory is high in impedance during the ninth clock pulse (acknowledge master).

The signal timing required for the operation of the I C Bus is summarized in figure 2.

Semiconductor Group

07.94

12 3 4 5 6 7...12

中文翻译

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