Datasheet > SCG3043

SCG3043

更新时间： 2024-11-22 01:24:43

品牌	Logo	应用领域
CONNOR-WINFIELD		ATM 异步传输模式电信电信集成电路
页数	文件大小	规格书
12页	750K
描述
Synchronous Clock Generators

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中文翻译

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数据手册

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SCG3043 数据手册

SCG3043

Synchronous Clock

Generators

PLL

2111 Comprehensive Drive

Aurora, Illinois 60505

Phone: 630-851-4722

Fax: 630- 851-5040

www.conwin.com

Application

Features

The SCG3043 is designed for use as a

reference input for OC-48 Framers and

SERDES. It generates less than 1 psRMS

jitter over the OC-48 bandwidth.

SCG3043 is well suited for use in line

cards, service termination cards and

similar functions to provide reliable

reference, phase locked, synchronization

for TDM, PDH, SONET, and SDH network

equipment. The SCG3043 provides a jitter

filtered, wander following output signal

synchronized to a superior Stratum or peer

input reference signal.

• 3.3V High

Precision PLL

• Two Differential

LVPECL Outputs

@ 155.52 MHz

• 77.76 MHz CMOS

Input Reference

• Reference Duty

Cycle Tolerant

• Low Temperature

Reflow Surface

Mounting

Bulletin

SG094

Page

1 of 12

Revision

P00

Date

17 NOV 04

Issued By

MBatts

12 3 4 5 6 7...12

中文翻译

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