Datasheet > SCG3050-155.52M

SCG3050-155.52M

更新时间： 2025-07-25 20:10:23

品牌	Logo	应用领域
CONNOR-WINFIELD		/
页数	文件大小	规格书
12页	790K
描述
Clock Generator, Hybrid, CDSO20

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数据手册

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SCG3050-155.52M 数据手册

SCG3050 Series

Synchronous Clock

Generators

PLL

2111 Comprehensive Drive

Aurora, Illinois 60505

Phone: 630-851-4722

Fax: 630- 851- 5040

www.conwin.com

Application

Features

• 3.3V High

The SCG3050 is designed for use as a

reference input for OC-48 Framers and

SERDES. It generates less than 1 psRMS

jitter over the OC-48 bandwidth.

SCG3050 is well suited for use in line

cards, service termination cards and

similar functions to provide reliable

reference, phase locked, synchronization

for TDM, PDH, SONET, and SDH network

equipment. The SCG3050 provides a jitter

filtered, wander following output signal

synchronized to a superior Stratum or peer

input reference signal.

Precision PLL

• Two Differential

LVPECL Outputs

@ 155.52 MHz

• 8 kHz CMOS

Input Reference

• Reference Duty

Cycle Tolerant

• Low Temperature

Reflow Surface

Mounting

Bulletin

SG032

Page

1 of 12

Revision

P01

Date

11 DEC 02

Issued By

MBatts

12 3 4 5 6 7...12

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