Datasheet > SCANPSC100FMW

SCANPSC100FMW

更新时间： 2024-01-17 00:50:15

品牌	Logo	应用领域
德州仪器 - TI		光电二极管外围集成电路
页数	文件大小	规格书
29页	416K
描述
SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28, SOIC-28

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SCANPSC100FMW 技术参数

生命周期：	Obsolete	包装说明：	SOP,
Reach Compliance Code：	unknown	HTS代码：	8542.31.00.01
风险等级：	5.62	JESD-30 代码：	R-PDSO-G28
长度：	17.9 mm	端子数量：	28
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
认证状态：	Not Qualified	座面最大高度：	2.65 mm
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	MILITARY
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	宽度：	7.5 mm
uPs/uCs/外围集成电路类型：	MICROPROCESSOR CIRCUIT	Base Number Matches：	1

SCANPSC100FMW 数据手册

September 1998

SCANPSC100F

Embedded Boundary Scan Controller

(IEEE 1149.1 Support)

General Description

Features

n Compatible with IEEE Std. 1149.1 (JTAG) Test Access

Port and Boundary Scan Architecture

The SCANPSC100F is designed to interface a generic paral-

lel processor bus to a serial scan test bus. It is useful in im-

proving scan throughput when applying serial vectors to sys-

tem test circuitry and reduces the software overhead that is

associated with applying serial patterns with a parallel pro-

cessor. The ’PSC100F operates by serializing data from the

parallel bus for shifting through the chain of 1149.1 compliant

components (i.e., scan chain). Scan data returning from the

scan chain is placed on the parallel port to be read by the

host processor. Up to two scan chains can be directly con-

trolled with the ’PSC100F via two independent TMS pins.

Scan control is supplied with user specific patterns which

makes the ’PSC100F protocol-independent. Overflow and

underflow conditions are prevented by stopping the test

clock. A 32-bit counter is used to program the number of TCK

cycles required to complete a scan operation within the

boundary scan chain or to complete a ’PSC100F Built-In Self

Test (BIST) operation. SCANPSC100F device drivers and

1149.1 embedded test application code are available with

National’s SCANEase software tools.

n Supported by National’s SCAN Ease (Embedded

Application Software Enabler) Software

n Uses generic, asynchronous processor interface;

compatible with a wide range of processors and PCLK

frequencies

n Directly supports up to two 1149.1 scan chains

n 16-bit Serial Signature Compaction (SSC) at the Test

Data In (TDI) port

n Automatically produces pseudo-random patterns at the

Test Data Out (TDO) port

n Fabricated on FACT 1.5 µm CMOS process

n Supports 1149.1 test clock (TCK) frequencies up to

25 MHz

n TTL-compatible inputs; full-swing CMOS outputs with

24 mA source/sink capability

™

n Standard Microcircuit Drawing (SMD) 5962-9475001

Connection Diagrams

28-Pin DIP and Flatpak

Pin Assignment for LCC

DS100325-18

DS100325-1

™

FACT is a trademark of Fairchild Semiconductor Corporation.

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

DS100325

www.national.com

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与SCANPSC100FMW相关器件

型号	品牌	描述	获取价格	数据表
SCANPSC100FSC	FAIRCHILD	Embedded Boundary Scan Controller (IEEE 1149.1 Support)	获取价格
SCANPSC100FSC	ROCHESTER	SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28, 0.300 INCH, MS-013, SOIC-28	获取价格
SCANPSC100FSCX	ROCHESTER	SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28, 0.300 INCH, MS-013, SOIC-28	获取价格
SCANPSC110	NSC	SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Suppo	获取价格
SCANPSC110F	NSC	SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Suppo	获取价格
SCANPSC110F	FAIRCHILD	SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Suppo	获取价格

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