Datasheet > SCANPSC100FMW

SCANPSC100FMW

更新时间： 2024-01-30 20:43:07

品牌	Logo	应用领域
德州仪器 - TI		光电二极管外围集成电路
页数	文件大小	规格书
29页	416K
描述
SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28, SOIC-28

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SCANPSC100FMW 技术参数

生命周期：	Obsolete	包装说明：	SOP,
Reach Compliance Code：	unknown	HTS代码：	8542.31.00.01
风险等级：	5.62	JESD-30 代码：	R-PDSO-G28
长度：	17.9 mm	端子数量：	28
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
认证状态：	Not Qualified	座面最大高度：	2.65 mm
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	MILITARY
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	宽度：	7.5 mm
uPs/uCs/外围集成电路类型：	MICROPROCESSOR CIRCUIT	Base Number Matches：	1

SCANPSC100FMW 数据手册

provide user specific control data. Test Data In (TDI) re-

ceives serial data from the scan chain. A local control block

is associated with each Shifter/Buffer to provide shift and

load control as well as providing full or empty status. The SSI

also provides Test Clock (TCK) Control. TCK is stopped and

started depending on the status of the Shifter/Buffers or the

32-bit Counter. By stopping and starting TCK, scan opera-

tions will proceed only when the enabled Shifter/Buffers are

ready to send and/or receive serial data.

Chip Architecture

The ’PSC100 is designed to act together with a parallel bus

host as a serial test bus master. Parallel data is written by the

host to the ’PSC100, which serializes the data for application

to a serial test bus. Serial data returning from the target scan

chain(s) is placed on the processor port for parallel reads.

Several features are included in the ’PSC100 which make

scan test communication more convenient and efficient.

Figure 1 shows the major functional blocks of the ’PSC100

design. The Parallel Processor Interface (PPI) is an asyn-

chronous, 8-bit parallel interface which is used by the host

processor to write and read data. The PPI generates the

necessary internal data, address, and control signals to

complete internal write and read operations.

The 32-bit Counter (CNT32) is a count-down binary counter

included to assist in controlling the SSI. The initial state of

CNT32 is loaded from the parallel port with four consecutive

writes to its address. When enabled, CNT32 is used to pro-

gram the number of TCKs applied by the SSI to the bound-

ary scan chain(s). The value of CNT32 can also be used to

generate interrupts (i.e., when CNT32 reaches terminal

count) and to trigger ’PSC100 features, such as, Auto TMS

High (discussed later within this datasheet).

The Serial Scan Interface (SSI) consists of

a bank of

double-buffered parallel/serial shift registers (i.e., a 2 x 8 bit

FIFO), or Shifter/Buffers. The double buffering improves effi-

ciency by allowing parallel writes or reads to/from one of the

two 8-bit FIFOs within the shifter/buffer while the other FIFO

is shifting data to/from the scan chain. Three Shifter/Buffers

are provided for outgoing serial data and one for incoming

serial data. Test Data Out (TDO) is for scanning out test data

while the two Test Mode Select signals (TMS0/1) are used to

The Mode and Status Registers are used to control and ob-

serve the operation of the SSI and CNT32. Each of the

Shifter/Buffers and CNT32 have an associated mode bit

which enables it for participation in on-going operations. Sta-

tus bits can be used for polling operations.

DS100325-2

FIGURE 1. ’PSC100 Block Diagram

Pin Descriptions

Description

Name

RST (Input)

The Reset pin is an asynchronous input that, when low, initializes the ’PSC100. Mode bits, Shifter/Buffer

and CNT32 control logic, TCK Control, and the PPI are all initialized to defined states. RST has hysteresis

for improved noise immunity.

SCK (Input)

OE (Input)

The System Clock drives all internal timing. The test clock, TCK, is a gated and buffered version of SCK.

SCK has hysteresis for improved immunity.

Output Enable TRI-STATEs all SSI outputs when high. A 20 kΩ pull-up resistor is connected to

automatically TRI-STATE^®these outputs when this signal is floating.

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与SCANPSC100FMW相关器件

型号	品牌	描述	获取价格	数据表
SCANPSC100FSC	FAIRCHILD	Embedded Boundary Scan Controller (IEEE 1149.1 Support)	获取价格
SCANPSC100FSC	ROCHESTER	SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28, 0.300 INCH, MS-013, SOIC-28	获取价格
SCANPSC100FSCX	ROCHESTER	SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28, 0.300 INCH, MS-013, SOIC-28	获取价格
SCANPSC110	NSC	SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Suppo	获取价格
SCANPSC110F	NSC	SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Suppo	获取价格
SCANPSC110F	FAIRCHILD	SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Suppo	获取价格

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