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SCANPSC100FMW PDF预览

SCANPSC100FMW

更新时间: 2024-02-13 16:55:27
品牌 Logo 应用领域
德州仪器 - TI 光电二极管外围集成电路
页数 文件大小 规格书
29页 416K
描述
SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28, SOIC-28

SCANPSC100FMW 技术参数

生命周期:Obsolete包装说明:SOP,
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.62JESD-30 代码:R-PDSO-G28
长度:17.9 mm端子数量:28
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
认证状态:Not Qualified座面最大高度:2.65 mm
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:7.5 mm
uPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUITBase Number Matches:1

SCANPSC100FMW 数据手册

 浏览型号SCANPSC100FMW的Datasheet PDF文件第2页浏览型号SCANPSC100FMW的Datasheet PDF文件第3页浏览型号SCANPSC100FMW的Datasheet PDF文件第4页浏览型号SCANPSC100FMW的Datasheet PDF文件第6页浏览型号SCANPSC100FMW的Datasheet PDF文件第7页浏览型号SCANPSC100FMW的Datasheet PDF文件第8页 
MODE1(4:3)  
MODE2(0)  
Mode and Status Registers (Continued)  
Bit 2 (Write Cycle):  
If set, will cause a pulse to be issued internally that  
will update all status bits. This bit will be reset upon  
completion of the pulse. The state of this bit is not  
readable. It is reset upon RST low.  
Parallel Processor Interface (PPI)  
ADDRESS ASSIGNMENT  
The following table defines which register is selected for ac-  
cess with the address lines, A(2:0).  
Bit 1: If set, will cause a synchronous reset of all func-  
tions except the parallel interface. The value of this  
bit will return to zero when the reset operation is  
complete.  
A2  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A1  
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A0  
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
R/W  
0
Function  
TDO Shifter/Buffer  
Counter Register 1  
TDI Shifter/Buffer  
TDI Shifter/Buffer  
TMS0 Shifter/Buffer  
Counter Register 2  
TMS1 Shifter/Buffer  
Counter Register 3  
32-Bit Counter  
Counter Register 0  
MODE0  
Bit 0: If set, will cause the 32-bit counter to count for one  
SCK cycle (no TCK cycle will be generated). The  
value of this bit will return to zero when the single  
step operation is complete.  
1
0
1
0
PROGRAMMING RESTRICTIONS  
1
Because certain mode bits enable shift operations for certain  
functions, these mode bits should not be changed when shift  
operations are in progress. The alignment of all registers  
during shift operations is controlled by a 3-bit counter in the  
TCK control block. Enabling or disabling a function in the  
middle of a shift operation may disrupt the logic necessary to  
keep all shifter/buffers byte-aligned.  
0
1
0
1
0
1
MODE0  
For example, if the TDO shifter/buffer (already loaded) is en-  
abled while the 3-bit counter value is 3, the shifter/buffer will  
only shift out only five bits of the first byte loaded.  
0
MODE1  
1
MODE1  
The following bits should not be changed when shift opera-  
tions are in progress, i.e., when TCK is enabled (see section  
on TCK Control).  
0
MODE2  
1
MODE2  
MODE0(7:3)  
5
www.national.com  

STM32F103C8T6 替代型号

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