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SCANPSC110F

更新时间： 2024-02-14 18:00:43

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		测试
页数	文件大小	规格书
25页	270K
描述
SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support)

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技术参数
数据手册

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SCANPSC110F 技术参数

生命周期：	Obsolete	包装说明：	QFF,
Reach Compliance Code：	unknown	HTS代码：	8542.31.00.01
风险等级：	5.62	JESD-30 代码：	R-GDFP-F28
长度：	18.8 mm	端子数量：	28
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	CERAMIC, GLASS-SEALED	封装代码：	QFF
封装形状：	RECTANGULAR	封装形式：	FLATPACK
认证状态：	Not Qualified	座面最大高度：	2.29 mm
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	MILITARY
端子形式：	FLAT	端子节距：	1.27 mm
端子位置：	DUAL	宽度：	9.145 mm
uPs/uCs/外围集成电路类型：	MICROPROCESSOR CIRCUIT	Base Number Matches：	1

SCANPSC110F 数据手册

March 1993

Revised August 2000

SCANPSC110F

SCAN Bridge Hierarchical and Multidrop Addressable

JTAG Port (IEEE1149.1 System Test Support)

General Description

Features

■ True IEEE1149.1 hierarchical and multidrop addressable

The SCANPSC110F Bridge extends the IEEE Std. 1149.1

test bus into a multidrop test bus environment. The advan-

tage of a hierarchical approach over a single serial scan

chain is improved test throughput and the ability to remove

a board from the system and retain test access to the

remaining modules. Each SCANPSC110F Bridge supports

up to 3 local scan rings which can be accessed individually

or combined serially. Addressing is accomplished by load-

ing the instruction register with a value matching that of the

Slot inputs. Backplane and inter-board testing can easily

be accomplished by parking the local TAP Controllers in

one of the stable TAP Controller states via a Park instruc-

tion. The 32-bit TCK counter enables built in self test oper-

ations to be performed on one port while other scan chains

are simultaneously tested.

capability

■ The 6 slot inputs support up to 59 unique addresses, a

Broadcast Address, and 4 Multi-cast Group Addresses

■ 3 IEEE 1149.1-compatible configurable local scan ports

■ Mode Register allows local TAPs to be bypassed,

selected for insertion into the scan chain individually, or

serially in groups of two or three

■ 32-bit TCK counter

■ 16-bit LFSR Signature Compactor

■ L4

■ local TAPs can be 3-stated via the OE input to allow an

alternate test master to take control of the local TAPs

Ordering Code:

Order Number

Package Number

Package Description

SCANPSC110FSC

M28B

28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Names

Description

TCK_B

Backplane Test Clock Input

TMS_B

TDI_B

TDO_B

TRST

S_(0,5)

Backplane Test Mode Select Input

Backplane Test Data Input

Backplane Test Data Output

Asynchronous Test Reset Input (Active LOW)

Address Select Port

Local Scan Port Output Enable (Active LOW)

TCK_L(1–3)Local Port Test Clock Output

TMS_L(1–3)Local Port Test Mode Select Output

TDI_L(1–3)Local Port Test Data Input

TDO_L(1–3)Local Port Test Data Output

DS011570

www.fairchildsemi.com

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与SCANPSC110F相关器件

型号	品牌	描述	获取价格	数据表
SCANPSC110FDM	NSC	暂无描述	获取价格
SCANPSC110FDMQB	NSC	SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Suppo	获取价格
SCANPSC110FE-QV	TI	SPECIALTY MICROPROCESSOR CIRCUIT, CQCC28, LCC-28	获取价格
SCANPSC110FFMQB	NSC	SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Suppo	获取价格
SCANPSC110FFMQB/NOPB	TI	SPECIALTY TELECOM CIRCUIT, CDFP28	获取价格
SCANPSC110FLMQB	NSC	SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Suppo	获取价格

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