Datasheet > SCANSTA101SMX

SCANSTA101SMX

更新时间： 2024-02-04 21:46:55

品牌	Logo	应用领域
美国国家半导体 - NSC		外围集成电路
页数	文件大小	规格书
31页	377K
描述
IC SPECIALTY MICROPROCESSOR CIRCUIT, PBGA49, BGA-49, Microprocessor IC:Other

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SCANSTA101SMX 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	BGA-49	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.02	JESD-30 代码：	S-PBGA-B49
JESD-609代码：	e0	长度：	7 mm
湿度敏感等级：	3	端子数量：	49
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFBGA
封装等效代码：	BGA49,7X7,32	封装形状：	SQUARE
封装形式：	GRID ARRAY, LOW PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	235
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	1.5 mm	子类别：	Other Microprocessor ICs
最大供电电压：	3.6 V	最小供电电压：	3 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	0.8 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	30	宽度：	7 mm
uPs/uCs/外围集成电路类型：	MICROPROCESSOR CIRCUIT	Base Number Matches：	1

SCANSTA101SMX 数据手册

October 2002

SCANSTA101

Low Voltage IEEE 1149.1 STA Master

General Description

Features

n Compatible with IEEE Std. 1149.1 (JTAG) Test Access

Port and Boundary Scan Architecture

The SCANSTA101 is designed to function as a test master

for a IEEE 1149.1 test system. The minimal requirements to

create a tester are a microcomputer (uP, RAM/ROM, clock,

etc.), SCANEASE r2.0 software, and a STA101.

n Supported by National’s SCAN Ease (Embedded

Application Software Enabler) Software Rev 2.0

n Available as a Silicon Device and Intellectual Property

(IP) model for embedding into VLSI devices

n Uses generic, asynchronous processor interface;

compatible with a wide range of processors and PCLK

frequencies

n 16-bit Data Interface (IP scalable to 32-bit)

n 2Kx32 bit dual-port memory addressing for access by

the PPI or the 1149.1 master

n Load-on-the-fly (LotF) and Preload operating modes

supported

n On-Board Sequencer allows multi-vector operations

such as those required to load data into an FPGA

n On-Board Compares support TDI validation against

preloaded expected data

The SCANSTA101 is an enhanced version of, and replace-

ment for, the SCANPSC100. The additional features of the

STA101 further allow it to offload some of the processor

overhead while remaining flexible. The device architecture

supports IEEE 1149.1, BIST, and IEEE 1532. The flexibility

will allow it to adapt to any changes that may occur in 1532

and support yet unknown variants.

The SCANSTA101 is useful in improving vector throughput

when applying serial vectors to system test circuitry and

reduces the software overhead that is associated with ap-

plying serial patterns with a parallel processor. The SCAN-

STA101 features a generic Parallel Processor Interface

(PPI) which operates by serializing data from the parallel bus

for shifting through the chain of 1149.1 compliant compo-

nents (i.e., scan chain). Writes can be controlled either by

wait states or the DTACK line. Handshaking is accomplished

with either polling or interrupts.

n 32-bit Linear Feedback Shift Register (LFSR) at the Test

Data In (TDI) port

n State, Shift, and BIST macros allow predetermined TMS

sequences to be utilized

n Operates at 3.3v supply voltages w/ 5V tolerant I/O

n Outputs support Power-Down TRI-STATE mode.

SCANSTA101 Architecture

10121502

FIGURE 1.

DS101215

www.national.com

12 3 4 5 6 7...31

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与SCANSTA101SMX相关器件

型号	品牌	描述	获取价格	数据表
SCANSTA101SMX/NOPB	TI	低电压 IEEE 1149.1 系统测试访问 (STA) 主设备 \| NZA \| 49 \|	获取价格
SCANSTA101W-QML	TI	SPECIALTY MICROPROCESSOR CIRCUIT, CQCC28, CERQUAD-48	获取价格
SCANSTA111	NSC	Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port	获取价格
SCANSTA111	TI	SCANSTA111 Enhanced SCAN Bridge	获取价格
SCANSTA111_05	NSC	Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port	获取价格
SCANSTA111MDC	TI	IC,TEST/JTAG SUPPORT,CMOS,DIE	获取价格

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