Datasheet > SCANSTA111MTX

SCANSTA111MTX

更新时间： 2024-02-26 11:23:51

品牌	Logo	应用领域
美国国家半导体 - NSC		光电二极管外围集成电路
页数	文件大小	规格书
31页	897K
描述
IC SPECIALTY MICROPROCESSOR CIRCUIT, PDSO48, TSSOP-48, Microprocessor IC:Other

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技术参数
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SCANSTA111MTX 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	TSSOP-48	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.08	JESD-30 代码：	R-PDSO-G48
JESD-609代码：	e0	长度：	12.5 mm
湿度敏感等级：	2	端子数量：	48
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装等效代码：	TSSOP48,.3,20	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	235
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	1.1 mm	子类别：	Other Microprocessor ICs
最大供电电压：	3.6 V	最小供电电压：	3 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	6.1 mm
uPs/uCs/外围集成电路类型：	MICROPROCESSOR CIRCUIT	Base Number Matches：	1

SCANSTA111MTX 数据手册

October 2005

SCANSTA111

Enhanced SCAN bridge

Multidrop Addressable IEEE 1149.1 (JTAG) Port

n 3 IEEE 1149.1-compatible configurable local scan ports

n Mode Register₀allows local TAPs to be bypassed,

selected for insertion into the scan chain individually, or

serially in groups of two or three

n Transparent Mode can be enabled with a single

instruction to conveniently buffer the backplane IEEE

1149.1 pins to those on a single local scan port

n LSP ACTIVE outputs provide local port enable signals

for analog busses supporting IEEE 1149.4.

n General purpose local port passthrough bits are useful

for delivering write pulses for FPGA programming or

monitoring device status.

General Description

The SCANSTA111 extends the IEEE Std. 1149.1 test bus

into a multidrop test bus environment. The advantage of a

multidrop approach over a single serial scan chain is im-

proved test throughput and the ability to remove a board

from the system and retain test access to the remaining

modules. Each SCANSTA111 supports up to

3 local

IEEE1149.1 scan rings which can be accessed individually

or combined serially. Addressing is accomplished by loading

the instruction register with a value matching that of the Slot

inputs. Backplane and inter-board testing can easily be ac-

complished by parking the local TAP Controllers in one of the

stable TAP Controller states via a Park instruction. The 32-bit

TCK counter enables built in self test operations to be per-

formed on one port while other scan chains are simulta-

neously tested.

n Known Power-up state

n TRST on all local scan ports

n 32-bit TCK counter

n 16-bit LFSR Signature Compactor

n Local TAPs can become TRI-STATE via the OE input to

allow an alternate test master to take control of the local

TAPs (LSP_0-2have a TRI-STATE notification output)

n 3.0-3.6V V_CCSupply Operation

Features

n True IEEE 1149.1 hierarchical and multidrop

addressable capability

n Power-off high impedance inputs and outputs

n Supports live insertion/withdrawal

n The 7 slot inputs support up to 121 unique addresses,

an Interrogation Address, Broadcast Address, and 4

Multi-cast Group Addresses (address 000000 is

reserved)

Connection Diagrams

10124516

10124502

DS101245

www.national.com

12 3 4 5 6 7...31

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与SCANSTA111MTX相关器件

型号	品牌	描述	获取价格	数据表
SCANSTA111MTX/NOPB	TI	Enhanced SCAN Bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port 48-TSSOP -40 to 85	获取价格
SCANSTA111MWC	TI	IC,TEST/JTAG SUPPORT,CMOS,DIE	获取价格
SCANSTA111SM	TI	SCANSTA111 Enhanced SCAN Bridge	获取价格
SCANSTA111SM	NSC	Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port	获取价格
SCANSTA111SM/NOPB	TI	Enhanced SCAN Bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port 49-NFBGA -40 to 85	获取价格
SCANSTA111SM/NOPB	NSC	IC SPECIALTY MICROPROCESSOR CIRCUIT, PBGA49, BGA-49, Microprocessor IC:Other	获取价格

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