Datasheet > SCANPSC100FMW

SCANPSC100FMW

更新时间： 2024-02-02 19:00:01

品牌	Logo	应用领域
德州仪器 - TI		光电二极管外围集成电路
页数	文件大小	规格书
29页	416K
描述
SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28, SOIC-28

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技术参数
数据手册

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SCANPSC100FMW 技术参数

生命周期：	Obsolete	包装说明：	SOP,
Reach Compliance Code：	unknown	HTS代码：	8542.31.00.01
风险等级：	5.62	JESD-30 代码：	R-PDSO-G28
长度：	17.9 mm	端子数量：	28
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
认证状态：	Not Qualified	座面最大高度：	2.65 mm
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	MILITARY
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	宽度：	7.5 mm
uPs/uCs/外围集成电路类型：	MICROPROCESSOR CIRCUIT	Base Number Matches：	1

SCANPSC100FMW 数据手册

Parallel Processor Interface (PPI) (Continued)

TIMING WAVEFORMS (Continued)

DS100325-5

FIGURE 4. Consecutive Read/Writes (best case timing)

DS100325-6

FIGURE 5. Consecutive Read/Writes (worst case timing)

Note 3: Figures 4, 5: Figure 4 shows the best case bus cycle timing for SCK and STB during consecutive read or write cycles. The rising edge of strobe occurs a

setup time, t or before the falling edge of SCK. This allows the cycle to be completed within 1.5 clock SCK clock cycles. Figure 5 shows the worst case bus cycle

timing for SCK and STB during consecutive read or write cycles. The rising edge of strobe does not meet the t requirement between STB and SCK. Therefore,

the propagation of the internal PSC100 control and reset signals is delayed until the next falling edge of SCK. The bus cycle is then completed 1.5 SCK cycles later

creating a total bus cycle time of 2.5 SCK cycles. If worst case timing is considered for bus cycle timing, t

is not a mandatory timing specification.

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