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SC16C554

更新时间: 2024-09-16 22:50:19
品牌 Logo 应用领域
恩智浦 - NXP 解码器先进先出芯片编码器
页数 文件大小 规格书
55页 268K
描述
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder

SC16C554 数据手册

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SC16C554/554D  
Quad UART with 16-byte FIFO and infrared (IrDA)  
encoder/decoder  
Rev. 05 — 10 May 2004  
Product data  
1. Description  
The SC16C554/554D is a 4-channel Universal Asynchronous Receiver and  
Transmitter (QUART) used for serial data communications. Its principal function is to  
convert parallel data into serial data and vice versa. The UART can handle serial data  
rates up to 5 Mbit/s. It comes with an Intel or Motorola interface.  
The SC16C554/554D is pin compatible with the ST16C554 and TL16C554 and it will  
power-up to be functionally equivalent to the 16C454. Programming of control  
registers enables the added features of the SC16C554/554D. Some of these added  
features are the 16-byte receive and transmit FIFOs, automatic hardware or software  
flow control and Infrared encoding/decoding. The selectable auto-flow control feature  
significantly reduces software overload and increases system efficiency while in FIFO  
mode by automatically controlling serial data flow using RTS output and CTS input  
signals. The SC16C554/554D also provides DMA mode data transfers through FIFO  
trigger levels and the TXRDY and RXRDY signals. On-board status registers provide  
the user with error indications, operational status, and modem interface control.  
System interrupts may be tailored to meet user requirements. An internal loop-back  
capability allows on-board diagnostics.  
The SC16C554/554D operates at 5 V, 3.3 V and 2.5 V, and the industrial temperature  
range, and is available in plastic PLCC68, LQFP64, and LQFP80 packages.  
2. Features  
5 V, 3.3 V and 2.5 V operation  
Industrial temperature range  
The SC16C554/554D is pin compatible with the industry-standard  
ST16C454/554, ST68C454/554, ST16C554, TL16C554  
Up to 5 Mbit/s data rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5 V  
16-byte transmit FIFO  
16-byte receive FIFO with error flags  
Automatic software/hardware flow control  
Programmable Xon/Xoff characters  
Software selectable Baud Rate Generator  
Four selectable Receive FIFO interrupt trigger levels  
Standard modem interface or infrared IrDA encoder/decoder interface  
Sleep mode  
Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun  
Break)  
Transmit, Receive, Line Status, and Data Set interrupts independently controlled  

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