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SB82434NX PDF预览

SB82434NX

更新时间: 2024-11-01 19:55:03
品牌 Logo 应用领域
英特尔 - INTEL PC动态存储器外围集成电路
页数 文件大小 规格书
191页 2636K
描述
DRAM Controller, 512M X 8, MOS, PQFP208, QFP-208

SB82434NX 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:FQFP,针数:208
Reach Compliance Code:unknown风险等级:5.84
地址总线宽度:32边界扫描:NO
总线兼容性:PCI; EISA; ISA; PENTIUM 610; PENTIUM 735; PENTIUM 815外部数据总线宽度:32
JESD-30 代码:S-PQFP-G208长度:28 mm
低功率模式:YES内存组织:512M X 8
区块数量:8端子数量:208
封装主体材料:PLASTIC/EPOXY封装代码:FQFP
封装形状:SQUARE封装形式:FLATPACK, FINE PITCH
认证状态:Not Qualified座面最大高度:3.75 mm
标称供电电压:5 V表面贴装:YES
技术:MOS端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:28 mmuPs/uCs/外围集成电路类型:MEMORY CONTROLLER, DRAM
Base Number Matches:1

SB82434NX 数据手册

 浏览型号SB82434NX的Datasheet PDF文件第2页浏览型号SB82434NX的Datasheet PDF文件第3页浏览型号SB82434NX的Datasheet PDF文件第4页浏览型号SB82434NX的Datasheet PDF文件第5页浏览型号SB82434NX的Datasheet PDF文件第6页浏览型号SB82434NX的Datasheet PDF文件第7页 
82434LX/82434NX PCI, CACHE AND MEMORY  
CONTROLLER (PCMC)  
Supports the PentiumTM Processor at  
iCOMPTM Index 510T60 MHz and iCOMP  
Index 567T66 MHz  
Supports the Pentium Processor at  
iCOMP Index 735T90 MHz, iCOMP Index  
815T100 MHz, and iCOMP Index 610T75  
MHz  
Integrated DRAM Controller  
Ð Supports 2 MBytes to 192 MBytes of  
Cacheable Main Memory for the  
82434LX  
Ð Supports 2 MBytes to 512 MBytes of  
Cacheable Main Memory for the  
82434NX  
Ð Supports DRAM Access Times of  
70 ns and 60 ns  
Ð CPU Writes Posted to DRAM 4-1-1-1  
Ð Refresh Cycles Decoupled from ISA  
Refresh to Reduce the DRAM  
Access Latency  
Y
Y
Y
Y
Y
Y
Supports Pipelined Addressing  
Capability of the Pentium Processor  
The 82430NX Drives 3.3V Signal Levels  
on the CPU and Cache Interfaces  
High Performance CPU/PCI/Memory  
Interfaces via Posted Write and Read  
Prefetch Buffers  
Ý
Ð Six RAS Lines (82434LX)  
Ð Eight RAS Lines (82434NX)  
Ý
Ý
Ð Refresh by RAS -Only, or CAS-  
Before-RAS , in Single or Burst  
Ý
Y
Y
Fully Synchronous PCI Interface with  
Full Bus Master Capability  
of Four  
Y
Host/PCI Bridge  
Ð Translates CPU Cycles into PCI Bus  
Cycles  
Supports the Pentium Processor  
Internal Cache in Either Write-Through  
or Write-Back Mode  
Ð Translates Back-to-Back Sequential  
CPU Memory Writes into PCI Burst  
Cycles  
Ð Burst Mode Writes to PCI in Zero PCI  
Wait-States (i.e. Data Transfer Every  
Cycle)  
Ð Full Concurrency Between CPU-to-  
Main Memory and PCI-to-PCI  
Transactions  
Ð Full Concurrency Between CPU-to-  
Second Level Cache and PCI-to-Main  
Memory Transactions  
Ð Same Cache and Memory System  
Logic Design for ISA and EISA  
Systems  
Ð Cache Snoop Filter Ensures Data  
Consistency for PCI-to-Main Memory  
Transactions  
Y
Programmable Attribute Map of DOS  
and BIOS Regions for System  
Flexibility  
Y
Y
Integrated Low Skew Clock Driver for  
Distributing Host Clock  
Integrated Second Level Cache  
Controller  
Ð Integrated Cache Tag RAM  
Ð Write-Through and Write-Back Cache  
Modes for the 82434LX  
Ð Write-Back for the 82434NX  
Ð 82434NX Supports Low-Power Cache  
Standby  
Ð Direct Mapped Organization  
Ð Supports Standard and Burst SRAMs  
Ð 256-KByte and 512-KByte Sizes  
Ð Cache Hit Cycle of 3-1-1-1 on Reads  
and Writes Using Burst SRAMs  
Ð Cache Hit Cycle of 3-2-2-2 on Reads  
and 4-2-2-2 on Writes Using  
Standard SRAMs  
Y
208-Pin QFP Package  
*Other brands and names are the property of their respective owners.  
December 1994  
Order Number: 290479-004  

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