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S8401QF/TD PDF预览

S8401QF/TD

更新时间: 2024-11-10 05:14:35
品牌 Logo 应用领域
AMCC 商用集成电路
页数 文件大小 规格书
18页 146K
描述
Consumer Circuit, Bipolar, PQFP52, 10 X 10 MM, PLASTIC, QFP-52

S8401QF/TD 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:QFP,针数:52
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.16商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:S-PQFP-G52长度:14 mm
功能数量:1端子数量:52
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装形状:SQUARE封装形式:FLATPACK
认证状态:Not Qualified座面最大高度:2.45 mm
最大压摆率:160 mA最大供电电压 (Vsup):3.47 V
最小供电电压 (Vsup):3.13 V表面贴装:YES
技术:BIPOLAR温度等级:COMMERCIAL
端子形式:GULL WING端子节距:1 mm
端子位置:QUAD宽度:14 mm
Base Number Matches:1

S8401QF/TD 数据手册

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®
DEVICE  
SPECIFICATION  
S8401/S8501  
HIGH DEFINITION SERIAL DIGITAL INTERFACE (HD-SDI) CHIPSET  
FEATURES  
GENERAL DESCRIPTION  
• Micro-Power Bipolor technology  
• SMPTE 292M compliant  
• 1.485 Gb/s or 1.485/1.001 Gb/s operation  
• HD-SDI Serializer transmitter incorporates a  
Phase Lock Loop (PLL) providing clock synthe-  
sis from low-speed reference  
The S8401 and S8501 transmitter and receiver pair  
are designed to perform HD-SDI over fiber optic or  
coaxial cable interfaces conforming to the require-  
ments of the SMPTE 292M. The chipset supports  
1.485 Gb/s with an associated 20-bit data word.  
The chipset performs parallel-to-serial and serial-to-  
parallel conversion for scrambled data. The S8401  
on-chip PLL synthesizes the high-speed clock from a  
low-speed reference. The S8501 on-chip PLL syn-  
chronizes directly to incoming digital signals, to receive  
the data stream. The transmitter and receiver each  
support differential PECL I/O for fiber optic compo-  
nent interfaces, to minimize crosstalk and maximize  
data integrity. Local loopback allows for system diag-  
nostics.  
• HD-SDI Deserializer receiver PLL configured  
for clock and data recovery  
• 20-bit parallel TTL compatible interface  
• Low-jitter serial PECL compatible interface  
• Lock detect  
• Local loopback  
• Continuous downstream clocking from receiver  
• Single +3.3V power supply  
• Compact 52 PQFP package  
APPLICATIONS  
Parallel to HD-SDI/HD-SDI to parallel interfacing  
• Compressors  
• Video graphics  
• Video editors  
The S8401 and S8501 operate from +3.3V power  
supplies. Each chip typically dissipates only 0.70 and  
0.90W respectively. Figure 1 shows a typical network  
configuration incorporating the chipset.  
• Disc storage devices  
• VTR’s  
• Cameras  
• Monitors  
• Frame synchronizers  
• Character generators  
Figure 1. System Block Diagram  
Coax  
or  
Fibre  
FPGA  
Descrambler  
Framer  
S8401  
HD-SDI  
Serializer  
S8501  
HD-SDI  
Deserializer  
20  
20  
FPGA  
Scrambler  
DRV  
EQ  
1
December 10, 1999 / Revision C  

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