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S6E1A11B0AGN20000 PDF预览

S6E1A11B0AGN20000

更新时间: 2024-09-16 00:48:31
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赛普拉斯 - CYPRESS 微控制器
页数 文件大小 规格书
96页 2332K
描述
32-bit ARM® Cortex®-M0FM0 Microcontroller

S6E1A11B0AGN20000 数据手册

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S6E1A Series  
32-bit ARM® Cortex®-M0+  
FM0+ Microcontroller  
The S6E1A Series is a series of highly integrated 32-bit microcontrollers designed for embedded controllers aiming at low power  
consumption and low cost.  
This series has the ARM Cortex-M0+ Processor with on-chip Flash memory and SRAM, and consists of peripheral functions such  
as various timers, ADCs and communication interfaces (UART, CSIO, I2C, LIN).  
The products which are described in this data sheet are placed into TYPE1-M0+ product categories in "FM0+ Family PERIPHERAL  
MANUAL".  
Features  
CSIO  
Full duplex double buffer  
32-bit ARM Cortex-M0+ Core  
Built-in dedicated baud rate generator  
Overrun error detection function  
Serial chip select function (ch.1 and ch.3 only)  
Data length: 5 to 16 bits  
Processor version: r0p1  
Maximum operating frequency: 40 MHz  
Nested Vectored Interrupt Controller (NVIC): 1 NMI  
(non-maskable interrupt) and 32 peripheral interrupt with 4  
selectable interrupt priority levels  
LIN  
LIN protocol Rev.2.1 supported  
Full duplex double buffer  
Master/Slave mode supported  
24-bit System timer (Sys Tick): System timer for OS task  
management  
LIN break field generation function (The length is variable  
between 13 bits and 16 bits.)  
Bit Band operation  
Compatible with Cortex-M3 bit band operation  
LIN break delimiter generation function (The length is  
variable between 1 bit and 4 bits.)  
Various error detection functions available (parity errors,  
framing errors, and overrun errors)  
On-Chip Memories  
Flash memory  
Up to 88 Kbyte  
I2C  
Standard-mode (Max: 100 kbps) supported / Fast-mode  
(Max 400kbps) supported.  
Read cycle:0 wait-cycle  
Security function for code protection  
SRAM  
The on-chip SRAM of this series has one independent SRAM.  
SRAM: 6 Kbyte  
Multi-function Serial Interface (Max 3channels)  
128 bytes with FIFO in all channels (The number of FIFO  
steps varies depending on the settings of the communication  
mode or bit length.)  
The operation mode of each channel can be selected from  
one of the following.  
UART  
CSIO  
LIN  
I2C  
UART  
Full duplex double buffer  
Parity can be enabled or disabled.  
Built-in dedicated baud rate generator  
External clock available as a serial clock  
Various error detection functions (parity errors, framing errors,  
and overrun errors)  
Cypress Semiconductor Corporation  
Document Number: 002-05091 Rev.*B  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised April 13, 2017  
 

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