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S3078DI PDF预览

S3078DI

更新时间: 2024-11-11 20:54:59
品牌 Logo 应用领域
AMCC ATM异步传输模式电信信息通信管理电信集成电路
页数 文件大小 规格书
24页 223K
描述
Clock Recovery Circuit, 1-Func, BICMOS, DIE-80

S3078DI 技术参数

生命周期:Obsolete零件包装代码:DIE
包装说明:DIE,针数:80
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.82JESD-30 代码:R-XUUC-N80
功能数量:1端子数量:80
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:DIE
封装形状:RECTANGULAR封装形式:UNCASED CHIP
认证状态:Not Qualified标称供电电压:3.3 V
表面贴装:YES技术:BICMOS
电信集成电路类型:ATM/SONET/SDH CLOCK RECOVERY CIRCUIT温度等级:INDUSTRIAL
端子形式:NO LEAD端子位置:UPPER
Base Number Matches:1

S3078DI 数据手册

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Part Number S3078  
Revision NC - December 22, 2000  
DEVICE SPECIFICATION  
S3078  
Multi-Rate Limiting Amplifier and Clock Recovery Unit  
Features  
General Description  
SiGe BiCMOS Technology  
The S3078 is a 3.3 V combined limiting amplifier and  
Clock Recovery Unit (CRU) for multi-rate applications.  
Figure 1 shows a typical network application.  
+3.3 V Power Supply  
Integrated Limiting Amplifier  
No Degradation in Jitter Tolerance down to  
5 mV Input  
The internal limiting amplifier provides a voltage limited  
signal into the CRU for inputs down to 5 mV. It has a  
Loss-of-Signal (LOS) output, which can be programmed  
to assert with input levels between 25 mVp-p and 60  
mVp-p. There is also an offset correction function that  
reduces pulse-width distortion.  
Loss-of-Signal Detection  
Supports Clock Recovery for:  
OC-48 (2488.32 Mbps) with FEC  
OC-24 (1244.16 Mbps) with FEC  
The CRU is implemented using AMCC's proven on-  
chip Phase Locked Loop (PLL) technology, and it can  
lock onto OC-48, OC-24, OC-12, GBE, FC, or OC-3  
scrambled NRZ signal with FEC capability up to 8  
bytes per 255-byte block, and recovers the clock from  
the data. It consists of a phase detector, a loop filter,  
and a Voltage Controlled Oscillator (VCO). The phase  
detector compares the phase relationship between the  
VCO output and the serial data input. A loop filter con-  
verts the phase detector output into a smooth DC  
voltage, and the DC voltage is input into the VCO  
whose frequency is varied by this voltage.  
OC-12 (622.08 Mbps) with FEC  
OC-3 (155.52 Mbps) with FEC NRZ data  
Gigabit Ethernet (GBE) (1250 Mbps) with FEC  
Fibre Channel (FC) (1062.5 Mbps) with FEC  
Fibre Channel (FC) (2125 Mbps) with FEC  
Lock Detect monitors frequency of  
incoming data  
Selectable reference frequencies  
155.52 MHz – 166.62 MHz or  
19.44 MHz – 20.83 MHz  
Typical power 730 mW  
81 Pin PBGA package and Die  
Figure 1. System Block Diagram  
S3049  
S3060  
S3078  
S3057  
S3057  
S3078  
S3060  
S3049  
1

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