Datasheet > S3092CB20

S3092CB20

更新时间： 2024-01-19 08:56:51

品牌	Logo	应用领域
AMCC		ATM 异步传输模式电信信息通信管理电信集成电路
页数	文件大小	规格书
21页	230K
描述
Receiver, 1-Func, BICMOS, CBGA148, CERAMIC, BGA-148

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S3092CB20 技术参数

生命周期：	Active	零件包装代码：	BGA
包装说明：	CERAMIC, BGA-148	针数：	148
Reach Compliance Code：	unknown	风险等级：	5.8
JESD-30 代码：	S-CBGA-B148	长度：	15 mm
负电源额定电压：	-5.2 V	功能数量：	1
端子数量：	148	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	BGA	封装形状：	SQUARE
封装形式：	GRID ARRAY	认证状态：	COMMERCIAL
座面最大高度：	3.1 mm	标称供电电压：	3.3 V
表面贴装：	YES	技术：	BICMOS
电信集成电路类型：	ATM/SONET/SDH RECEIVER	温度等级：	COMMERCIAL
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	宽度：	15 mm
Base Number Matches：	1

S3092CB20 数据手册

Part Number S3092

Revision A – February 22, 2002

DEVICE SPECIFICATION

S3092

SONET/SDH/ATM OC-192 1:16 Receiver with CDR and Postamp

FEATURES

GENERAL DESCRIPTION

•

Silicon Germanium BiCMOS technology

The S3092 SONET/SDH receiver chip is a fully inte-

grated deserializer/CDR with SONET OC-192 with FEC

and Digital Wrapper (9.953 Gbps to 10.709 Gbps) rate

capability. The S3092 receives an OC-192 scrambled

NRZ signal and recovers the clock from the data. The

chip performs all necessary serial-to-parallel functions in

conformance with SONET/SDH/Digital Wrapper trans-

mission standards. The device is suitable for SONET-

based ATM applications. Figure 1 shows a typical net-

work application.

Complies with Telcordia, ITU-T, and G.709

specifications

•

Integrated Phase Lock Loop

OC-192 with FEC and Digital Wrapper (DW)

(9.953 to 10.709 Gbps)

Reference frequency of 155.52 MHz

(or equivalent FEC or DW rate)

•

16-bit parallel, 622.08 Mbps (or equivalent FEC

or DW rate) LVDS data path

The S3092 is a fully integrated OC-192/STM-64 Clock

and Data Recovery (CDR) and demultiplexer (DeMUX).

The S3092 recovers a synchronous signal from the

incoming 9.953 Gbps to 10.709 Gbps serial NRZ data

stream and re-times and demultiplexes the serial data

into 16 parallel 622.08 Mbps (or equivalent FEC or DW

rate) lines. The IC detects a Loss-of-Signal condition,

outputs a stable 622.08 MHz (or equivalent FEC or DW

rate) clock when the serial data is lost, and provides

1:16 demultiplexing. It also has a limiting postamp on

the serial input for small signal gain.

•

Lock detect

Low jitter CML differential serial interface

Dual +3.3 V and -5.2 V power supply

Performs clock recovery for 9.953 Gbps

(or equivalent FEC or DW rate) serial NRZ data

•

Synthesizes parallel output clock during loss-

of-signal conditions

•

Postamp on serial input

148-pin CBGA package

Typical power dissipation 2.2 W

The chip can be used with a 155.52 MHz (or equiva-

lent FEC or DW rate) reference clock. The low jitter

LVDS interface guarantees compliance with the bit-

error rate requirements of the Bellcore and ITU-T

standards.

APPLICATIONS

•

SONET/SDH-based transmission systems

SONET/SDH modules

SONET/SDH test equipment

ATM over SONET/SDH

Section repeaters

Add Drop Multiplexers (ADM)

Broad-band cross-connects

Fiber optic terminators

Fiber optic test equipment

Figure 1. System Block Diagram

INDUS

S3091

OTX

ORX

OTX

S3092

(19201),

GANGES

(19202)

HUDSON

(19203)

(19201),

GANGES

(19202)

HUDSON

(19203)

S3092

S3091

12 3 4 5 6 7...21

中文翻译

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