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S29WS064RABBHI013

更新时间： 2023-07-15 00:00:00
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
83页 2362K
描述
Flash, 4MX16, 80ns, PBGA84, 11.60 X 8 MM, HALOGEN FREE AND LEAD FREE, FPBGA-84

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S29WS064RABBHI013 数据手册

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D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )  
1. General Description  
The Spansion S29WS064R is a 64 Megabit 1.8 Volt-only MirrorBit Flash memory organized as 4,194,304  
words of 16 bits each. This burst mode Flash device is capable of performing simultaneous read and write  
operations with zero latency on two separate banks using separate data and address pins. This device can  
operate up to 108 MHz and uses a single VCC of 1.7V to 1.95V to read, program, and erase the memory  
array, making it ideal for today's demanding applications requiring higher density, better performance and  
lowered power consumption. A 9.0-volt ACC may be used for faster program performance if desired. This  
device can also be programmed in standard EPROM programmers.  
The device operates within the temperature range of -40°C to +85°C or -25°C to +85°C, and is offered in a  
Very Thin FBGA package.  
1.1  
Simultaneous Read/Write Operations with Zero Latency  
The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space  
into four banks. The device allows a host system to program or erase in one bank, then immediately and  
simultaneously read from another bank, with zero latency. This releases the system from waiting for the  
completion of program or erase operations. The devices are structured as shown in the following tables:  
Table 1.1 Device Structure (Top Boot)  
S29WS064R  
Bank  
Sector Size  
32 Kwords  
32 Kwords  
32 Kwords  
32 Kwords  
8 Kwords  
Sector Count  
0
1
2
32  
32  
32  
31  
4
3
Table 1.2 Device Structure (Bottom Boot)  
S29WS064R  
Sector Size  
8 Kwords  
Bank  
Sector Count  
4
0
32 Kwords  
32 Kwords  
32 Kwords  
32 Kwords  
31  
32  
32  
32  
1
2
3
The VersatileIO™ (VIO) control allows the host system to set the voltage levels that the device generates at  
its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the  
VIO pin.  
The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Output Enable (OE#) to  
control asynchronous read and write operations. For burst operations, the device additionally requires Ready  
(RDY) and Clock (CLK). This implementation allows easy interface with minimal glue logic to  
microprocessors/micro controllers for high performance read operations.  
The devices offer complete compatibility with the JEDEC 42.4 single-power-supply Flash command set  
standard. Commands are written to the command register using standard microprocessor write timings.  
Reading data out of the device are similar to reading from other Flash or EPROM devices.  
The host system can detect whether a program or erase operation is complete by using the device status bit  
DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the  
device automatically returns to reading array data.  
September 30, 2010 S29WS064R_00_03  
S29WS064R  
5
12345678...83

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