S29WS128J/064J
128/64 Megabit (8/4 M x 16-Bit)
CMOS 1.8 Volt-only Simultaneous Read/Write,
Burst Mode Flash Memory
Data Sheet
Distinctive Characteristics
Architectural Advantages
Hardware Features
Single 1.8 volt read, program and erase (1.65 to
1.95 volt)
Handshaking feature available
— Provides host system with minimum possible latency
by monitoring RDY
Manufactured on 0.11 µm process technology
Hardware reset input (RESET#)
— Hardware method to reset the device for reading
array data
Simultaneous Read/Write operation
— Data can be continuously read from one bank while
executing erase/program functions in other bank
— Zero latency between read and write operations
— Four bank architecture: WS128J: 16Mb/48Mb/48Mb/
16Mb, WS064J: 8Mb/24Mb/24Mb/8Mb
WP# input
— Write protect (WP#) function allows protection of
four outermost boot sectors, regardless of sector
protect status
Programable Burst Interface
Persistent Sector Protection
— 2 Modes of Burst Read Operation
— Linear Burst: 8, 16, and 32 words with wrap-around
— Continuous Sequential Burst
— A command sector protection method to lock
combinations of individual sectors and sector groups
to prevent program or erase operations within that
sector
Secured Silicon Sector region
— 128 words accessible through a command sequence,
64words for the Factory Secured Silicon Sector and
64words for the Customer Secured Silicon Sector.
Sector Architecture
4 Kword x 16 boot sectors, eight at the top of the address
range, and eight at the bottom of the address range
— Sectors can be locked and unlocked in-system at VCC
level
Password Sector Protection
— A sophisticated sector protection method to lock
combinations of individual sectors and sector groups
to prevent program or erase operations within that
sector using a user-defined 64-bit password
— WS128J: 4 Kword X 16, 32 Kword x 254 sectors
Bank A : 4 Kword x 8, 32 Kword x 31 sectors
ACC input: Acceleration function reduces
programming time; all sectors locked when ACC =
VIL
Bank B : 32 Kword x 96 sectors
Bank C : 32 Kword x 96 sectors
Bank D : 4 Kword x 8, 32 Kword x 31 sectors
CMOS compatible inputs, CMOS compatible outputs
Low VCC write inhibit
— WS064J: 4 Kword x 16, 32 Kword x 126 sectors.
Bank A : 4 Kword x 8, 32 Kword x 15 sectors
Software Features
Bank B : 32 Kword x 48 sectors
Supports Common Flash Memory Interface (CFI)
Bank C : 32 Kword x 48 sectors
Bank D : 4 Kword x 8, 32 Kword x 15 sectors
Software command set compatible with JEDEC
42.4 standards
— Backwards compatible with Am29BDS, Am29BDD,
Am29BL, and MBM29BS families
WS128J : 84-ball (8 mm x 11.6 mm) FBGA package,
WS064J : 80-ball (7 mm x 9 mm) FBGA package
Cyclling Endurance : 1,000,000 cycles per sector
typical
Data# Polling and toggle bits
— Provides a software method of detecting program
and erase operation completion
Data retention : 20-years typical
Erase Suspend/Resume
— Suspends an erase operation to read data from, or
program data to, a sector that is not being erased,
then resumes the erase operation
Performance Characteristics
Read access times at 80/66 MHz
— Synchronous latency of 71/56 ns (at 30 pF)
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
— Asynchronous random access times of 55/55 ns (at
30 pF)
Power dissipation (typical values, CL = 30 pF)
— Burst Mode Read: 18 mA @ 80Mhz
— Simultaneous Operation: 60 mA @ 80Mhz
— Program/Erase: 15 mA
— Standby mode: 0.2 µA
Publication Number S29WS-J_00 Revision A Amendment 6 Issue Date May 11, 2006
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion LLC deems the products to have been in sufficient
production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to
the valid combinations offered may occur.