S25FL256L/S25FL128L
256Mbit (32Mbyte)/128Mbit (16Mbyte),
3.0 V FL-L Flash Memory
General Description
The Cypress FL-L Family devices are Flash non-volatile memory products using:
– Floating Gate technology
– 65 nm process lithography
The FL-L family connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output
(Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit wide Quad I/O (QIO) and Quad Peripheral
Interface (QPI) commands. In addition, there are Double Data Rate (DDR) read commands for QIO and QPI that transfer address
and read data on both edges of the clock.
The architecture features a Page Programming Buffer that allows up to 256-bytes to be programmed in one operation and provides
individual 4KB sector, 32KB half block, 64KB block, or entire chip erase.
By using FL-L family devices at the higher clock rates supported, with Quad commands, the instruction read transfer rate can match
or exceed traditional parallel interface, asynchronous, NOR Flash memories, while reducing signal count dramatically.
The FL-L family products offer high densities coupled with the flexibility and fast performance required by a variety of mobile or
embedded applications. Provides an ideal storage solution for systems with limited space, signal connections, and power. These
memories offer flexibility and performance well beyond ordinary serial flash devices. They are ideal for code shadowing to RAM,
executing code directly (XIP), and storing re-programmable data.
Features
Serial Peripheral Interface (SPI) with Multi-I/O
– Clock polarity and phase modes 0 and 3
– Double Data Rate (DDR) option
– Status and Configuration Register Protection
– Four Security Regions of 256 bytes each outside the main
Flash array
– Legacy Block Protection: Block range
– Individual and Region Protection
– Quad peripheral Interface (QPI) option
– Extended Addressing: 24- or 32-bit address options
– Serial Command subset and footprint compatible with
S25FL-A, S25FL1-K, S25FL-P, S25FL-S and S25FS-S SPI
families
– Multi I/O Command subset and footprint compatible with
S25FL-P, S25FL-S and S25FS-S SPI families
– Individual Block Lock: Volatile individual Sector/Block
– Pointer Region: Non-Volatile Sector/Block range
– Power Supply Lock-down, Password, or Permanent
protection of Security Regions 2 and 3 and Pointer
Region
Read
Technology
– Commands: Normal, Fast, Dual I/O, Quad I/O, DualO,
QuadO, DDR Quad I/O.
– Modes: Burst Wrap, Continuous (XIP), QPI
– Serial Flash Discoverable Parameters (SFDP) for
configuration information.
– 65 nm Floating Gate Technology
Single Supply Voltage with CMOS I/O
– 2.7 V to 3.6 V
Temperature Range / Grade
– Industrial (–40°C to +85°C)
Program Architecture
– Industrial Plus (–40°C to +105°C)
– Automotive, AEC-Q100 Grade 3 (–40°C to +85°C)
– Automotive, AEC-Q100 Grade 2 (–40°C to +105°C)
– Automotive, AEC-Q100 Grade 1 (–40°C to +125°C)
– 256 Bytes Page Programming buffer3.0 V FL-L Flash
Memory
– Program suspend and resume
Erase Architecture
Packages (all Pb-free)
– Uniform 4KB Sector Erase
– Uniform 32KB Half Block Erase
– Uniform 64KB Block Erase
– Chip erase
– 8-pin SOIC 208 mil (SOC008) — S25FL128L only
– WSON 5 6 mm (WND008) — S25FL128L only
– WSON 6 8 mm (WNG008) — S25FL256L only
– 16-pin SOIC 300 mil (SO3016)
– Erase suspend and resume
100,000 Program/Erase Cycles, minimum
20 Year Data Retention, minimum
Security features
– BGA-24 6 8 mm
– 5 5 ball (FAB024) footprint
– 4 6 ball (FAC024) footprint
Cypress Semiconductor Corporation
Document Number: 002-00124 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 07, 2017
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