RTL8306SD/RTL8306SDM
Datasheet
Table of Contents
1.
2.
3.
4.
5.
GENERAL DESCRIPTION..............................................................................................................................................1
FEATURES.........................................................................................................................................................................3
SYSTEM APPLICATIONS...............................................................................................................................................4
BLOCK DIAGRAM...........................................................................................................................................................5
PIN ASSIGNMENTS .........................................................................................................................................................6
5.1.
5.2.
5.3.
PIN ASSIGNMENTS DIAGRAM.......................................................................................................................................6
PACKAGE IDENTIFICATION...........................................................................................................................................6
PIN ASSIGNMENTS TABLE............................................................................................................................................7
6.
PIN DESCRIPTIONS.........................................................................................................................................................9
6.1.
MEDIA CONNECTION PINS ...........................................................................................................................................9
MODE CONFIGURATION PINS .......................................................................................................................................9
PORT4 MAC CIRCUIT INTERFACE PINS......................................................................................................................13
PORT 4 PHY CIRCUIT INTERFACE PINS......................................................................................................................16
MISCELLANEOUS PINS ...............................................................................................................................................23
PORT LED PINS .........................................................................................................................................................24
SERIAL EEPROM AND SMI PINS ..............................................................................................................................26
STRAPPING PINS.........................................................................................................................................................27
PORT STATUS STRAPPING PINS ..................................................................................................................................29
POWER PINS...............................................................................................................................................................31
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
6.10.
7.
BASIC FUNCTIONAL DESCRIPTION........................................................................................................................32
7.1.
SWITCH CORE FUNCTION OVERVIEW.........................................................................................................................32
7.1.1. Dual MII/RMII .....................................................................................................................................................32
7.1.2. Port0, 1, 2, 3 Status Configuration.......................................................................................................................35
7.1.3. Flow Control ........................................................................................................................................................35
7.1.4. Address Search, Learning, and Aging..................................................................................................................37
7.1.5. Half Duplex Operation.........................................................................................................................................38
7.1.6. InterFrame Gap....................................................................................................................................................38
7.1.7. Illegal Frame........................................................................................................................................................38
7.2.
PHYSICAL LAYER FUNCTIONAL OVERVIEW...............................................................................................................39
7.2.1. Auto-Negotiation for UTP ....................................................................................................................................39
7.2.2. 10Base-T Transmit Function................................................................................................................................39
7.2.3. 10Base-T Receive Function..................................................................................................................................39
7.2.4. Link Monitor.........................................................................................................................................................39
7.2.5. 100Base-TX Transmit Function............................................................................................................................39
7.2.6. 100Base-TX Receive Function..............................................................................................................................40
7.2.7. Power-Down Mode...............................................................................................................................................40
7.2.8. Crossover Detection and Auto Correction ...........................................................................................................40
7.2.9. Polarity Detection and Correction.......................................................................................................................41
7.3.
GENERAL FUNCTION OVERVIEW................................................................................................................................42
7.3.1. Reset .....................................................................................................................................................................42
7.3.2. Setup and Configuration.......................................................................................................................................43
7.3.3. Serial EEPROM Example: 24LC01/02/04 ...........................................................................................................44
7.3.4. SMI .......................................................................................................................................................................46
7.3.5. Head-Of-Line Blocking ........................................................................................................................................47
7.3.6. Filtering/Forwarding Reserved Control Frame...................................................................................................47
7.3.7. Loop Detection .....................................................................................................................................................48
7.3.8. MAC Local Loopback Return to External ............................................................................................................49
6-port 10/100Mbps Single-Chip Dual MII/RMII Switch Controller
iii
Track ID: JATR-1076-21 Rev. 1.1
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