RTL8306SD/RTL8306SDM
Datasheet
List of Tables
TABLE 1. PIN ASSIGNMENTS TABLE ..............................................................................................................................................7
TABLE 2. MEDIA CONNECTION PINS..............................................................................................................................................9
TABLE 3. MODE CONFIGURATION PIN DEFINITIONS......................................................................................................................9
TABLE 4. PORT4 MAC CIRCUIT INTERFACE PINS........................................................................................................................13
TABLE 5. PORT 4 PHY CIRCUIT INTERFACE PIN DEFINITIONS.....................................................................................................16
TABLE 6. MISCELLANEOUS PINS .................................................................................................................................................23
TABLE 7. PORT LED PINS............................................................................................................................................................24
TABLE 8. SERIAL EEPROM AND SMI PINS.................................................................................................................................26
TABLE 9. STRAPPING PINS...........................................................................................................................................................27
TABLE 10. PORT STATUS STRAPPING PINS ....................................................................................................................................29
TABLE 11. POWER PINS.................................................................................................................................................................31
TABLE 12. DUALMII/RMII MODE CONFIGURATION TABLE .......................................................................................................34
TABLE 13. SMI READ/WRITE CYCLES ..........................................................................................................................................46
TABLE 14. RESERVED ETHERNET MULTICAST ADDRESSES...........................................................................................................47
TABLE 15. LOOP FRAME FORMAT.................................................................................................................................................48
TABLE 16. AN EXAMPLE USING POWER TRANSISTOR 2SB1188 ...................................................................................................51
TABLE 17. ADVANCED FUNCTION DESCRIPTION...........................................................................................................................52
TABLE 18. CPU TAG FORMAT ......................................................................................................................................................63
TABLE 19. MIB COUNTER TIMEOUT .............................................................................................................................................68
TABLE 20. CPU TAG FORMAT ......................................................................................................................................................73
TABLE 21. BIT TO PORT MAPPING IN CPU TAG ............................................................................................................................73
TABLE 22. IEEE 802.1X MAC-BASED ENTRY..............................................................................................................................76
TABLE 23. BEHAVIOR ON TX_EN, RX_EN, AND PSTAN.............................................................................................................77
TABLE 24. BEHAVIOR ACCORDING TO EN_INPUT, EN_BRO_INPUT, EN_MUL_INPUT, EN_UDA_INPUT ......................................78
TABLE 25. SPD AND BI-COLOR LINK/ACT TRUTH TABLE WHEN RTL8306SD/RTL8306SDM CONTROLLING LED....................83
TABLE 26. BI-COLOR LED TRUTH TABLE WHEN CPU CONTROLLING LED.................................................................................84
TABLE 27. REGISTER DESCRIPTIONS.............................................................................................................................................85
TABLE 28. PHY 0 REGISTER 0 (PAGE 0, 1, 2, 3): CONTROL...........................................................................................................87
TABLE 29. PHY 0 REGISTER 1 (PAGE 0, 1, 2, 3): STATUS..............................................................................................................88
TABLE 30. PHY 0 REGISTER 2 (PAGE 0, 1, 2, 3): PHY IDENTIFIER 1.............................................................................................88
TABLE 31. PHY 0 REGISTER 3 (PAGE 0, 1, 2, 3): PHY IDENTIFIER 2.............................................................................................89
TABLE 32. PHY 0 REGISTER 4 (PAGE 0, 1, 2, 3): AUTO-NEGOTIATION ADVERTISEMENT .............................................................89
TABLE 33. PHY 0 REGISTER 5 (PAGE 0, 1, 2, 3): AUTO-NEGOTIATION LINK PARTNER ABILITY...................................................90
TABLE 34. PHY 0 REGISTER 16 (PAGE 0, 1, 2, 3): GLOBAL CONTROL 0........................................................................................91
TABLE 35. PHY 0 REGISTER 18 (PAGE 0, 1): GLOBAL CONTROL 2 ...............................................................................................92
TABLE 36. PHY 0 REGISTER 19 (PAGE 0,1): GLOBAL CONTROL 3................................................................................................92
TABLE 37. PHY 0 REGISTER 22 (PAGE 0, 1): PORT 0 CONTROL REGISTER 0.................................................................................93
TABLE 38. PHY 0 REGISTER 24 (PAGE 0,1): PORT 0 CONTROL REGISTER 1..................................................................................94
TABLE 39. PHY 1 REGISTER 24 (PAGE 0,1): PORT 1 CONTROL REGISTER 1..................................................................................95
TABLE 40. PHY 2 REGISTER 23 (PAGE 0,1): GLOBAL OPTION REGISTER 1...................................................................................97
TABLE 41. PHY 2 REGISTER 24(PAGE 0,1): PORT 2 CONTROL REGISTER 2 ..................................................................................97
TABLE 42. PHY 3 REGISTER 16 (PAGE 0, 1, 2, 3): SWITCH MAC ADDRESS ..................................................................................98
TABLE 43. PHY 3 REGISTER 17~18 (PAGE 0, 1): SWITCH MAC ADDRESS ...................................................................................99
TABLE 44. PHY 3 REGISTER 24 (PAGE 0, 1): PORT 3 CONTROL REGISTER 1.................................................................................99
TABLE 45. PHY 4 REGISTER 24 (PAGE 0, 1): PORT 4 CONTROL REGISTER 1...............................................................................101
TABLE 46. PHY 5 REGISTER 0 (PAGE 0, 1, 2, 3): CONTROL.........................................................................................................102
TABLE 47. PHY 5 REGISTER 1 (PAGE 0, 1, 2, 3): STATUS............................................................................................................103
TABLE 48. PHY 5 REGISTER 2 (PAGE 0, 1, 2, 3): PHY IDENTIFIER 1...........................................................................................103
TABLE 49. PHY 5 REGISTER 3 (PAGE 0, 1, 2, 3): PHY IDENTIFIER 2...........................................................................................103
TABLE 50. PHY 5 REGISTER 4 (PAGE 0, 1, 2, 3): AUTO-NEGOTIATION ADVERTISEMENT ...........................................................104
TABLE 51. PHY 5 REGISTER 5 (PAGE 0, 1, 2, 3): AUTO-NEGOTIATION LINK PARTNER ABILITY.................................................105
TABLE 52. PHY 6 REGISTER 0 (PAGE 0, 1, 2, 3): CONTROL.........................................................................................................106
6-port 10/100Mbps Single-Chip Dual MII/RMII Switch Controller
vii
Track ID: JATR-1076-21 Rev. 1.1
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