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RM48L950ZWT PDF预览

RM48L950ZWT

更新时间： 2024-11-24 08:43:55
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德州仪器 - TI /
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179页 8824K
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RISC MICROCONTROLLER

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RM48L950ZWT 数据手册

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Sample &  
Buy  
Support &  
Community  
Product  
Folder  
Tools &  
Software  
Technical  
Documents  
RM48L950, RM48L750, RM48L550  
SPNS174C –APRIL 2012–REVISED JUNE 2015  
RM48Lx50 16- and 32-Bit RISC Flash Microcontroller  
1 Device Overview  
1.1 Features  
1
• High-Performance Microcontroller for Safety-  
Critical Applications  
• Multiple Communication Interfaces  
– 10/100 Mbps Ethernet MAC (EMAC)  
– Dual CPUs Running in Lockstep  
– ECC on Flash and RAM Interfaces  
•
•
IEEE 802.3 Compliant (3.3-V I/O Only)  
Supports MII, RMII, and MDIO  
– Built-In Self-Test (BIST) for CPU and On-chip  
RAMs  
– Error Signaling Module With Error Pin  
– Voltage and Clock Monitoring  
– USB  
•
•
2-Port USB Host Controller  
One Full-Speed USB Device Port  
– Three CAN Controllers (DCANs)  
• ARM® Cortex®-R4F 32-Bit RISC CPU  
– Efficient 1.66 DMIPS/MHz With 8-Stage Pipeline  
– FPU With Single- and Double-Precision  
– 12-Region Memory Protection Unit (MPU)  
– Open Architecture With Third-Party Support  
• Operating Conditions  
•
•
64 Mailboxes, Each With Parity Protection  
Compliant to CAN Protocol Version 2.0B  
– Standard Serial Communication Interface (SCI)  
– Local Interconnect Network (LIN) Interface  
Controller  
•
•
Compliant to LIN Protocol Version 2.1  
Can be Configured as a Second SCI  
– System Clock up to 200 MHz  
– Inter-Integrated Circuit (I2C)  
– Core Supply Voltage (VCC): 1.2 V Nominal  
– I/O Supply Voltage (VCCIO): 3.3 V Nominal  
– ADC Supply Voltage (VCCAD): 3.0 to 5.25 V  
• Integrated Memory  
– Three Multibuffered Serial Peripheral Interfaces  
(MibSPIs)  
•
128 Words With Parity Protection Each  
– 3MB of Program Flash With ECC (RM48L950)  
– 2MB of Program Flash With ECC  
(RM48L750/550)  
– 256KB of RAM With ECC (RM48L950/750)  
– 192KB of RAM With ECC (RM48L550)  
– 64KB of Flash With ECC for Emulated  
EEPROM  
– Two Standard Serial Peripheral Interfaces  
(SPIs)  
• Two Next Generation High-End Timer (N2HET)  
Modules  
– N2HET1: 32 Programmable Channels  
– N2HET2: 18 Programmable Channels  
– 160-Word Instruction RAM Each With Parity  
Protection  
• 16-Bit External Memory Interface  
– Each N2HET Includes Hardware Angle  
Generator  
– Dedicated High-End Transfer Unit (HTU) With  
MPU for Each N2HET  
• Common Platform Architecture  
– Consistent Memory Map Across Family  
– Real-Time Interrupt (RTI) Timer OS Timer  
– 96-Channel Vectored Interrupt Module (VIM)  
– 2-Channel Cyclic Redundancy Checker (CRC)  
• Direct Memory Access (DMA) Controller  
– 16 Channels and 32 Peripheral Requests  
– Parity Protection for Control Packet RAM  
– DMA Accesses Protected by Dedicated MPU  
• Two 12-Bit Multibuffered ADC Modules  
– ADC1: 24 Channels  
– ADC2: 16 Channels Shared With ADC1  
– 64 Result Buffers With Parity Protection Each  
• General-Purpose Input/Output (GPIO) Pins  
Capable of Generating Interrupts  
– 16 Pins on the ZWT Package  
– 10 Pins on the PGE Package  
• IEEE 1149.1 JTAG, Boundary Scan and ARM  
CoreSight™ Components  
• JTAG Security Module  
• Packages  
• Frequency-Modulated Phase-Locked Loop  
(FMPLL) With Built-In Slip Detector  
• Separate Nonmodulating PLL  
• Trace and Calibration Capabilities  
– Embedded Trace Macrocell (ETM-R4)  
– Data Modification Module (DMM)  
– RAM Trace Port (RTP)  
– 144-Pin Quad Flatpack (PGE) [Green]  
– 337-Ball Grid Array (ZWT) [Green]  
– Parameter Overlay Module (POM)  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
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 		Vdss (V) : 100V;Id @ 25C (A) : 48 A;Rds-on (typ) (mOhms) : 11.3 mOhms;Total Gate Charge (n

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