Datasheet > RM24EP64

RM24EP64

更新时间： 2024-09-17 01:11:15

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
17页	818K
描述
32/64/128-Kbit 2.7V Minimum Sterilization-Tolerant Boot Memory

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RM24EP64 数据手册

RM24EP32 | RM24EP64 | RM24EP128

32/64/128-Kbit 2.7V Minimum

Sterilization-Tolerant Boot Memory

I²C Bus

Preliminary Datasheet

Features



Gamma Radiation Tolerance: 50 kGy

e-Beam Sterilization Tolerance: 50 kGy

Memory array: 32-Kbit, 64-Kbit, and 128-Kbit EEPROM-compatible boot memory

Single supply voltage: 2.7V - 3.6V

2-wire I²C interface

Compatible with I²C bus modes:

-100kHz

-400kHz

-1MHz



Page size: 32 byte / 64 byte

-Byte and Page Write from 1 to 32 or 64 bytes

-Byte Write within 50µs

-Page Write within 1ms



Random and sequential Read modes

Write protect of the whole memory array

RoHS-compliant and halogen-free packaging

Based on Adesto's proprietary CBRAM^®technology

Description

The RM24EP I²C EEPROM-compatible family of gamma-tolerant boot memory is

comprised of devices with densities of 32 Kbit, 64 Kbit and 128 Kbit utilizing Adesto's

CBRAM resistive memory technology. The memory devices use a single low-voltage

supply ranging from 2.7V to 3.6V.

The Adesto I C device is accessed through a 2-wire I C compatible interface

consisting of a Serial Data (SDA) and Serial Clock (SCL). The maximum clock (SCL)

frequency is 1MHz.

The devices have both byte write and page write capability. Page write is up to 32/64

bytes.

Both random and sequential reads are available. Sequential reads are capable of

reading the entire memory in one operation.

External address pins permit up to eight devices on the same data bus. The devices

are available in standard 8-pin SOIC packages.

DS-RM24EP–048C–6/2014

12 3 4 5 6 7...17

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