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QL5064-66BPB456C PDF预览

QL5064-66BPB456C

更新时间: 2024-02-09 19:44:07
品牌 Logo 应用领域
其他 - ETC 总线控制器
页数 文件大小 规格书
37页 764K
描述
BUS CONTROLLER

QL5064-66BPB456C 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:BGA, BGA456,26X26,50
针数:456Reach Compliance Code:compliant
ECCN代码:3A001.A.3HTS代码:8542.31.00.01
风险等级:5.88Is Samacsys:N
地址总线宽度:64总线兼容性:PCI
最大时钟频率:66 MHz最大数据传输速率:533 MBps
驱动器接口标准:IEEE 1149.1A外部数据总线宽度:64
JESD-30 代码:S-PBGA-B456JESD-609代码:e0
长度:35 mm湿度敏感等级:3
端子数量:456最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA456,26X26,50
封装形状:SQUARE封装形式:GRID ARRAY
峰值回流温度(摄氏度):250电源:3.3,3.3/5 V
认证状态:Not Qualified座面最大高度:2.52 mm
子类别:Bus Controllers最大压摆率:100 mA
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:40宽度:35 mm
uPs/uCs/外围集成电路类型:BUS CONTROLLER, PCIBase Number Matches:1

QL5064-66BPB456C 数据手册

 浏览型号QL5064-66BPB456C的Datasheet PDF文件第2页浏览型号QL5064-66BPB456C的Datasheet PDF文件第3页浏览型号QL5064-66BPB456C的Datasheet PDF文件第4页浏览型号QL5064-66BPB456C的Datasheet PDF文件第5页浏览型号QL5064-66BPB456C的Datasheet PDF文件第6页浏览型号QL5064-66BPB456C的Datasheet PDF文件第7页 
QL5064 QuickPCI Data Sheet  
66 MHz/64-bit PCI Master/Target with Embedded Programmable  
Logic and dual Port SRAM  
• • • • • •  
1.0 Device Highlights  
High Performance PCI Controller  
Extremely Flexible and Configurable  
64-bit / 66 MHz Master/Target PCI  
Controller (automatically backwards  
compatible to 33 MHz or/and 32-bits)  
Supports processor-less systems, as well as 0  
wait-state burst connections to all known  
8/16/32/64 bit processors  
75 MHz PCI Interface supported for  
Includes non-volatile on-chip configuration  
embedded systems  
data for total customization  
PCI Specification v2.2 compliance  
Independent PCI bus (66 MHz) and local bus  
(100 MHz) clocks  
Programmable back-end interface with three  
64-bit busses/100 MHz  
All local interface, control, and glue-logic can  
be implemented on chip  
Provides full 533 MB/s PCI data transfer  
rates (600 MB/s at 75 MHz)  
“PCI friendly” pinout simplifies board layout,  
supports 4-layer PCI boards  
Advanced PCI Features  
Advanced Master DMA Features  
DMA Chaining mode for queued DMA  
transactions  
Programmable DMA Channel Arbitration  
Scheme  
Four-channel DMA mastering, plus a SPCI  
(Single PCI Access) mode  
SPCI (Single PCI Access) mode may initiate  
any PCI Master command  
Unlimited bursts supported in Master and  
Target mode  
DMA controller configurable via PCI or  
back-end  
Two Master Write FIFOs and two Master  
Read FIFOs, each 64-deep and 64 bits wide  
DMA Chaining mode allows a linked list of  
DMA transfers to occur without user  
intervention  
Target Read and Write FIFOs for pre-fetched  
reads and multipleposted writes  
Programmable interrupt controller  
High Performance PCI Target  
I2O compliant under microprocessor control  
16 Mailbox registers for message passing and  
Write posting FIFO increases performance  
with queued transactions  
semaphores  
Extended configuration space allowing  
Messaged Interrupts,  
(up to 16 queued writes)  
Any BAR can be defined as pre-fetchable  
power management, and future PCI  
enhancement support  
Six base address registers supported,  
configurable as memory or IO  
Unique “Target Blast Mode” enables high-  
performance and very low overhead  
streaming data to/from PCI  
QL5064 QuickPCI Data Sheet Rev D  
1

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