Datasheet > QL6250PS484

QL6250PS484

更新时间： 2024-02-08 07:14:48

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
13页	164K
描述
ASIC

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技术参数
数据手册

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QL6250PS484 技术参数

生命周期：	Contact Manufacturer	Reach Compliance Code：	compliant
风险等级：	5.84

QL6250PS484 数据手册

Eclipse Family Data Sheet

Combining Performance, Density and Embedded RAM

• • • • • •

1.0 Device Highlights

Flexible Programmable Logic

Programmable I/O

• .25u, 5 layer metal CMOS process

• 2.5 V Vcc, 2.5/3.3 V drive capable I/O

• Up to 4032 SuperCells

• High performance Enhanced I/O (EIO):

Less than 3 ns Tco

• Programmable Slew Rate Control

• Programmable I/O Standards

• Up to 583,000 Max System Gates

• Up to 512 I/O

• LVTTL, LVCMOS, PCI, GTL+, SSTL2,

and SSTL3

• 8 Independent I/O Banks

Embedded Dual Port SRAM

• 3 Register Configuration: Input, Output, OE

• Up to 36-2,304 bit Dual Port High

• performance SRAM Blocks

• Up to 82,900 RAM bits

Advanced Clock Network

• 9 Global Clock Networks

• 1 dedicated

• RAM/ROM/FIFO Wizard for automatic

configuration

• 8 programmable

• Configurable and Cascadable

• 16 I/O (high drive) Networks:

2 I/O’s per bank

Applications

• 20 Quad-Net Networks: 5 per quadrant

• Signal processing operators

• Signal processing functions

• Networking / communications for VoIP

• Speech / voice processing

• Channel coding

Figure 1: Embedded Eclipse Block Diagram

•

Eclipse^TMFamily Data Sheet

12 3 4 5 6 7...13

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