Datasheet > QL4036-0PQ208C

QL4036-0PQ208C

更新时间： 2024-11-10 23:30:39

品牌	Logo	应用领域
其他 - ETC		现场可编程门阵列可编程逻辑栅时钟
页数	文件大小	规格书
12页	199K
描述
Field Programmable Gate Array (FPGA)

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QL4036-0PQ208C 数据手册

QL4036 - QuickRAM^TM

36,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density, and Embedded RAM

QL4036 - QuickRAM

EVICE

HIGHLIGHTS

Device Highlights

High Performance & High Density

■ 36,000 Usable PLD Gates with 204 I/Os

672

High Speed

Logic Cells

14 RAM

Blocks

}

■ 300 MHz 16-bit Counters, 400 MHz Datapaths,

160+ MHz FIFOs

■ 0.35µm four-layer metal non-volatile CMOS process for

smallest die sizes

Interface

FIGURE 1. QuickRAM Block Diagram

High Speed Embedded SRAM

■ 14 dual-port RAM modules, organized in user-config-

urable 1,152 bit blocks

RCHITECTURE

VERVIEW

■ 5ns access times, each port independently accessible

■ Fast and effecient for FIFO, RAM, and ROM functions

Architecture Overview

The QuickRAM family of ESPs (Embedded Standard

Products) offers FPGA logic in combination with Dual-

Port SRAM modules. The QL4036 is a 36,000

usable PLD gate member of the QuickRAM family of

ESPs. QuickRAM ESPs are fabricated on a 0.35mm

four-layer metal process using QuickLogic’s patented

ViaLink^TMtechnology to provide a unique combina-

tion of high performance, high density, low cost, and

extreme ease-of-use.

Easy to Use / Fast Development Cycles

■ 100% routable with 100% utilization and complete

pin-out stability

■ Variable-grain logic cells provide high performance and

100% utilization

■ Comprehensive design tools include high quality

Verilog/VHDL synthesis

The QL4036 contains 672 logic cells and 14 dual

port RAM modules (see Figure 1). Each RAM module

has 1,152 RAM bits, for a total of 16,128 bits. RAM

Modules are Dual Port (one read port, one write port)

and can be configured into one of four modes: 64

(deep) x18 (wide), 128x9, 256x4, or 512x2 (see Fig-

ure 2). With a maximum of 204 I/Os, the QL4036 is

available in 144-pin TQFP, 208-pin PQFP and 256-

pin PBGA packages.

Advanced I/O Capabilities

■ Interfaces with both 3.3V and 5.0V devices

■ PCI compliant with 3.3V and 5.0V busses for -1/-2/-3/-4

speed grades

■ Full JTAG boundary scan

■ Registered I/O cells with individually controlled clocks and

output enables

Designers can cascade multiple RAM modules to

increase the depth or width allowed in single modules

by connecting corresponding address lines together

and dividing the words between modules (see Figure

3). This approach allows up to 512-deep configura-

tions as large as 16 bits wide in the smallest Quick-

RAM device and 44 bits wide in the largest device.

6-31

QL4036 Rev F

12 3 4 5 6 7...12

中文翻译

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与QL4036-0PQ208C相关器件

型号	品牌	获取价格	描述	数据表
QL4036-0PQ208I	ETC	获取价格	Field Programmable Gate Array (FPGA)
QL4036-0PQ208M	ETC	获取价格	90,000 Usable PLD Gate QuickRAM Combining Performance, Density and Embedded RAM
QL4036-0PQ208M/883	ETC	获取价格	90,000 Usable PLD Gate QuickRAM Combining Performance, Density and Embedded RAM
QL4036-0PQ240M	ETC	获取价格	90,000 Usable PLD Gate QuickRAM Combining Performance, Density and Embedded RAM
QL4036-0PQ240M/883	ETC	获取价格	90,000 Usable PLD Gate QuickRAM Combining Performance, Density and Embedded RAM
QL4036-1CF100M	ETC	获取价格	90,000 Usable PLD Gate QuickRAM Combining Performance, Density and Embedded RAM
QL4036-1CF100M/883	ETC	获取价格	90,000 Usable PLD Gate QuickRAM Combining Performance, Density and Embedded RAM
QL4036-1CF208M	ETC	获取价格	90,000 Usable PLD Gate QuickRAM Combining Performance, Density and Embedded RAM
QL4036-1CF208M/883	ETC	获取价格	90,000 Usable PLD Gate QuickRAM Combining Performance, Density and Embedded RAM
QL4036-1CG144M	ETC	获取价格	90,000 Usable PLD Gate QuickRAM Combining Performance, Density and Embedded RAM

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