Datasheet > QL3025-1PB256M

QL3025-1PB256M

更新时间： 2024-09-15 23:30:39

品牌	Logo	应用领域
其他 - ETC		现场可编程门阵列可编程逻辑栅时钟
页数	文件大小	规格书
10页	180K
描述
Field Programmable Gate Array (FPGA)

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QL3025-1PB256M 数据手册

QL3025 - pASIC 3 FPGA^TM

25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density

QL3025 - pASIC 3 FPGA

EVICE

IGHLIGHTS

Device Highlights

High Performance & High Density

■ 25,000 Usable PLD Gates with 204 I/Os

■ 16-bit counter speeds over 300 MHz, data path speeds over

400 MHz

■ 0.35um four-layer metal non-volatile CMOS process for

smallest die sizes

Easy to Use / Fast Development Cycles

■ 100% routable with 100% utilization and complete

pin-out stability

■ Variable-grain logic cells provide high performance and

100% utilization

■ Comprehensive design tools include high quality

Verilog/VHDL synthesis

FIGURE 1. 672 Logic Cells

Advanced I/O Capabilites

■ Interfaces with both 3.3 volt and 5.0 volt devices

■ PCI compliant with 3.3V and 5.0V buses for -1/-2/-3/-4

RODUCT

UMMARY

speed grades

■ Full JTAG boundary scan

Product Summary

■ Registered I/O cells with individually controlled clocks and

The QL3025 is a 25,000 usable PLD gate member of

the pASIC 3 family of FPGAs. pASIC 3 FPGAs are

fabricated on a 0.35mm four-layer metal process

using QuickLogic’s patented ViaLink technology to

provide a unique combination of high performance,

high density, low cost, and extreme ease-of-use.

output enables

Total of 204 I/O Pins

■ 196 bidirectional input/output pins, PCI-compliant for 5.0 volt

and 3.3 volt buses for -1/-2/-3/-4 speed grades

■ 4 high-drive input-only pins

■ 4 high-drive input/distributed network pins

The QL3025 contains 672 logic cells. With a

maximum of 204 I/Os, the QL3025 is available in

144-pin TQFP, 208-PQFP, and 256-pin PBGA

packages.

Four Low-Skew Distributed Networks

■ Two array clock/control networks available to the logic cell flip-

flop clock, set and reset inputs - each driven by an input-only pin

■ Six global clock/control networks available to the logic cell F1,

clock set and reset inputs and the input and I/O register clock,

reset and enable inputs as well as the output enable control - each

driven by an input-only or I/O pin, or any logic cell output or I/O

cell feedback

Software support for the complete pASIC 3 family,

including the QL3025, is available through three basic

packages. The turnkey QuickWorks“ package

provides the most complete FPGA software solution

from design entry to logic synthesis, to place and

route, to simulation. The QuickTools^TMfor

Workstations package provides a solution for

designers who use Cadence, Exemplar, Mentor,

Synopsys, Synplicity, Viewlogic, Veribest, or other

third-party tools for design entry, synthesis, or

simulation.

High Performance

■ Input + logic cell + output total delays under 6 ns

■ Data path speeds over 400 MHz

■ Counter speeds over 300 MHz

QL3025 Rev C

7-27

12 3 4 5 6 7...10

中文翻译

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与QL3025-1PB256M相关器件

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QL30251PF144C	ETC	获取价格	25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density
QL3025-1PF144C	ETC	获取价格	Field Programmable Gate Array (FPGA)
QL30251PF144I	ETC	获取价格	25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density
QL3025-1PF144I	ETC	获取价格	Field Programmable Gate Array (FPGA)
QL30251PF144M	ETC	获取价格	25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density
QL3025-1PF144M	ETC	获取价格	Field Programmable Gate Array (FPGA)
QL3025-1PL84M	ETC	获取价格	60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density
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QL3025-1PQ208C	ETC	获取价格	Field Programmable Gate Array (FPGA)
QL30251PQ208I	ETC	获取价格	25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density

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