5秒后页面跳转
QL3012-0PL84M PDF预览

QL3012-0PL84M

更新时间: 2024-11-01 06:06:15
品牌 Logo 应用领域
其他 - ETC 可编程逻辑
页数 文件大小 规格书
14页 239K
描述
60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density

QL3012-0PL84M 数据手册

 浏览型号QL3012-0PL84M的Datasheet PDF文件第2页浏览型号QL3012-0PL84M的Datasheet PDF文件第3页浏览型号QL3012-0PL84M的Datasheet PDF文件第4页浏览型号QL3012-0PL84M的Datasheet PDF文件第5页浏览型号QL3012-0PL84M的Datasheet PDF文件第6页浏览型号QL3012-0PL84M的Datasheet PDF文件第7页 
Military Plastic pASIC 3 Family  
60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density  
Military pASIC 3 - 3.3V Family  
D
EVICE  
H
IGHLIGHTS  
FEATURES  
Features  
Device Highlights  
Total of 180 I/O pins  
High Performance and High Density  
308 bidirectional input/output pins, PCI-compliant  
for 5.0 volt and 3.3 volt buses for -1/-2 speed  
grades  
60,000 Usable PLD Gates with 316 I/Os  
16-bit counter speeds over 300 MHZ, data path  
speeds over 400 MHz  
8 high-drive input/distributed network pins  
0.35um four-layer metal non-volatile CMOS  
process for smallest die sizes  
Eight Low-Skew Distributed Networks  
Two array clock/control networks available to the  
logic cell flip-flop clock, set and reset inputs - each  
driven by an input-only pin  
Easy to Use/Fast Development Cycles  
100% routable with 100% utilization and complete  
pin-out stability  
Up to six global clock/control networks available  
to the logic cell F1, clock, set and reset inputs and  
the input and I/O register clock, reset and enable  
inputs as well as the output enable control - each  
driven by an input-only or I/O pin, or any logic cell  
output or I/O cell feedback  
Variable-grain logic cells provide high performance  
and 100% utilization  
Comprehensive design tools include high quality  
Verilog/VHDL synthesis  
Advanced I/O Capabilities  
Interfaces with both 3.3 volt and 5.0 volt devices  
High Performance  
Input + logic cell + output total delays under 6 ns  
Data path speeds exceeding 400 MHz  
Counter speeds over 300 MHz  
PCI compliant with 3.3V and 5.0V buses for -1/-2  
speed grades  
Full JTAG boundary scan  
Registered I/O cells with individually controlled  
clocks and output enables  
ASIC  
Gates  
PLD  
Gates  
Max  
I/O  
Qualification  
Level  
Supply  
Voltage  
Device  
Package  
QL3012  
QL3025  
QL3040  
QL3060  
8,000  
16,000  
24,000  
36,000  
12,000  
25,000  
40,000  
60,000  
84PLCC  
68  
M
M
M
M
3.3V  
3.3V  
3.3V  
3.3V  
208PQFP 174  
208PQFP 174  
208PQFP 174  
M = Military Temperature (-55 to +125 degrees C)  
TABLE 1: Selector Table  
Rev B  
8-23  

与QL3012-0PL84M相关器件

型号 品牌 获取价格 描述 数据表
QL3012-0PQ208M ETC

获取价格

60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density
QL3012-1PF100C ETC

获取价格

Field Programmable Gate Array (FPGA)
QL3012-1PF100I ETC

获取价格

Field Programmable Gate Array (FPGA)
QL3012-1PF100M ETC

获取价格

Field Programmable Gate Array (FPGA)
QL3012-1PF144C ETC

获取价格

Field Programmable Gate Array (FPGA)
QL3012-1PF144I ETC

获取价格

Field Programmable Gate Array (FPGA)
QL3012-1PF144M ETC

获取价格

Field Programmable Gate Array (FPGA)
QL3012-1PL84C ETC

获取价格

Field Programmable Gate Array (FPGA)
QL3012-1PL84I ETC

获取价格

Field Programmable Gate Array (FPGA)
QL3012-1PL84M ETC

获取价格

Field Programmable Gate Array (FPGA)