Military Plastic pASIC 3 Family
60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density
Military pASIC 3 - 3.3V Family
D
EVICE
H
IGHLIGHTS
FEATURES
Features
Device Highlights
Total of 180 I/O pins
High Performance and High Density
■ 308 bidirectional input/output pins, PCI-compliant
for 5.0 volt and 3.3 volt buses for -1/-2 speed
grades
■ 60,000 Usable PLD Gates with 316 I/Os
■ 16-bit counter speeds over 300 MHZ, data path
speeds over 400 MHz
■ 8 high-drive input/distributed network pins
■ 0.35um four-layer metal non-volatile CMOS
process for smallest die sizes
Eight Low-Skew Distributed Networks
■ Two array clock/control networks available to the
logic cell flip-flop clock, set and reset inputs - each
driven by an input-only pin
Easy to Use/Fast Development Cycles
■ 100% routable with 100% utilization and complete
pin-out stability
■ Up to six global clock/control networks available
to the logic cell F1, clock, set and reset inputs and
the input and I/O register clock, reset and enable
inputs as well as the output enable control - each
driven by an input-only or I/O pin, or any logic cell
output or I/O cell feedback
■ Variable-grain logic cells provide high performance
and 100% utilization
■ Comprehensive design tools include high quality
Verilog/VHDL synthesis
Advanced I/O Capabilities
■ Interfaces with both 3.3 volt and 5.0 volt devices
High Performance
■ Input + logic cell + output total delays under 6 ns
■ Data path speeds exceeding 400 MHz
■ Counter speeds over 300 MHz
■ PCI compliant with 3.3V and 5.0V buses for -1/-2
speed grades
■ Full JTAG boundary scan
■ Registered I/O cells with individually controlled
clocks and output enables
ASIC
Gates
PLD
Gates
Max
I/O
Qualification
Level
Supply
Voltage
Device
Package
QL3012
QL3025
QL3040
QL3060
8,000
16,000
24,000
36,000
12,000
25,000
40,000
60,000
84PLCC
68
M
M
M
M
3.3V
3.3V
3.3V
3.3V
208PQFP 174
208PQFP 174
208PQFP 174
M = Military Temperature (-55 to +125 degrees C)
TABLE 1: Selector Table
Rev B
8-23