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Q67100-Q2148 PDF预览

Q67100-Q2148

更新时间: 2024-02-03 00:15:27
品牌 Logo 应用领域
英飞凌 - INFINEON 动态存储器
页数 文件大小 规格书
24页 1309K
描述
3.3V 256 K x 16-Bit EDO-DRAM 3.3V 256 K x 16-Bit EDO-DRAM Low power version with Self Refresh

Q67100-Q2148 数据手册

 浏览型号Q67100-Q2148的Datasheet PDF文件第2页浏览型号Q67100-Q2148的Datasheet PDF文件第3页浏览型号Q67100-Q2148的Datasheet PDF文件第4页浏览型号Q67100-Q2148的Datasheet PDF文件第5页浏览型号Q67100-Q2148的Datasheet PDF文件第6页浏览型号Q67100-Q2148的Datasheet PDF文件第7页 
3.3V 256 K x 16-Bit EDO-DRAM  
HYB 314175BJ-50/-55/-60  
HYB 314175BJL-50/-55/-60  
3.3V 256 K x 16-Bit EDO-DRAM  
(Low power version with Self Refresh)  
Preliminary Information  
262 144 words by 16-bit organization  
0 to 70 °C operating temperature  
Fast access and cycle time  
Low Power dissipation  
max. 450 mW active (-50 version)  
max. 432 mW active (-55 version)  
max. 378 mW active (-60 version)  
Standby power dissipation  
7.2 mW standby (TTL)  
RAS access time:  
50 ns (-50 version)  
55 ns (-55 version)  
60 ns (-60 version)  
3.6 mW max. standby (CMOS)  
0.72 mW max. standby (CMOS) for  
Low Power Version  
CAS access time:  
13ns (-50 & -55 version)  
15 ns (-60 version)  
Output unlatched at cycle end allows two-  
dimensional chip selection  
Read, write, read-modify write, CAS-  
before-RAS refresh, RAS-only refresh,  
hidden-refresh and hyper page (EDO)  
mode capability  
Cycle time:  
89 ns (-50 version)  
94 ns (-55 version)  
104 ns (-60 version)  
Hype page mode (EDO) cycle time  
20 ns (-50 & -55 version)  
25 ns (-60 version)  
2 CAS / 1 WE control  
Self Refresh (L-Version)  
All inputs and outputs TTL-compatible  
512 refresh cycles / 16 ms  
512 refresh cycles / 128 ms  
Low Power Version only  
High data rate  
50 MHz (-50 & -55 version)  
40 MHz (-60 version)  
Plastic Packages:  
Single + 3.3 V (±0.3 V) supply with a built-  
P-SOJ-40-1 400mil width  
in VBB generator  
The HYB 314175BJ/BJL is the new generation dynamic RAM organized as 262 144 words by  
16-bit. The HYB 314175BJ/BJL utilizes CMOS silicon gate process as well as advanced circuit  
techniques to provide wide operation margins, both internally and for the system user. Multiplexed  
address inputs permit the HYB 314175BJ/BJL to be packed in a standard plastic 400mil wide  
P-SOJ-40-1 package. This package size provides high system bit densities and is compatible with  
commonly used automatic testing and insertion equipment. System oriented features include Self  
Refresh (L-Version), single + 3.3 V (± 0.3 V) power supply, direct interfacing with high performance  
logic device families.  
Semiconductor Group  
1
7.96  

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