Datasheet > Q67100-H5096

Q67100-H5096

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
英飞凌 - INFINEON		存储可编程只读存储器
页数	文件大小	规格书
12页	143K
描述
Nonvolatile Memory 4-Kbit E2PROM with I2C Bus Interface

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Q67100-H5096 数据手册

Nonvolatile Memory 4-Kbit E²PROM

with I²C Bus Interface

SDA 2546-5

Preliminary Data

MOS IC

Features

● Word-organized reprogrammable nonvolatile memory

in n-channel floating-gate technology (E PROM)

● 512 × 8-bit organization

● Supply voltage 5 V

● Serial 2-line bus for data input and output (I C Bus)

● Reprogramming mode, 10 ms erase/write cycle

● Reprogramming by means of on-chip control (without

external control)

P-DIP-8-1

● The end of the programming cycle can be checked

● Data retention in excess of 10 years

● More than 10 reprogramming cycles per address

Type

Ordering Code

Package

SDA 2546-5

Q67100-H5096

P-DIP-8-1

Circuit Description

I C Bus Interface

The I C Bus is a bidirectional 2-line bus for the transfer of data between various integrated circuits.

It consists of a data line SDA and a clock line SCL. The data line requires an external pull-up resistor

to V_CC(open drain output stages).

The possible operational states of the I C Bus are shown in figure 1. In the quiescent state, both

lines SDA and SCL are high, i.e. the output states are disabled. As long as SCL remains "1",

information changes on the data bus indicate the start or the end of a data transfer between two

components. The transition on SDA from "1" to "0" is a start condition, the transition from "0" to "1"

a stop condition. During a data transfer the information on the data bus will only change when the

clock line SCL is "0". The information on SDA is valid as long as SCL is "1".

In conjunction with an I C Bus system, the device can operate as a receiver, and as a transmitter

(slave receiver/listener, or slave transmitter/talker). Between the falling edge of the eighth

transmission pulse and a ninth acknowledge clock pulse, the device sets the SDA-line to low as a

reception confirmation, if the chip select conditions have been met. During the output of data, the

data output of the memory becomes high, during the ninth clock pulse (acknowledge master).

The signal timing required for the operation of the I C Bus is summarized in figure 2.

Semiconductor Group

07.94

12 3 4 5 6 7...12

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