Datasheet > Q67100-H5096

Q67100-H5096

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
英飞凌 - INFINEON		存储可编程只读存储器
页数	文件大小	规格书
12页	143K
描述
Nonvolatile Memory 4-Kbit E2PROM with I2C Bus Interface

阅读下载

获取价格

如果您发现信息不准确，欢迎纠错

Q67100-H5096 数据手册

SDA 2546-5

Control Functions of the I C Bus

The device is controlled by the controller (master) via I C Bus in two operating modes: real cycle,

and reprogramming cycle, including erase and write to a memory address. In both operating modes,

the controller, as transmitter, has to provide 3 bytes to the bus after the start condition. Each byte

has to be followed by an acknowledge bit. During a memory read, at least eight additional clock

pulses are required to accept the data from the memory, before the stop condition may follow. In the

programming case, the active programming process is only started by the stop condition after data

input, see figure 3.

The chip select word includes the chip select bit CS. Thus is possible to parallel two memory

devices. Chip select is obtained when the control bits logically correspond to the condition selected

at the select input CS. The most significant bits A8 and A9 are inputs with the chip select words

CS/E.

Checking the End of the Programming Cycle and Breaking off the Programming Cycle

Addressing the chip by the input of CS/E during active reprogramming terminates the programming

cycle. If the chip is addressed by entering CS/A, this will be ignored. Only when the programming

cycle has terminated will the chip react on CS/A. With this procedure the end of the programming

cycle can be checked, see figure 3.

Memory Read

After the input of the two control words CS/E and WA, the resetting of the start condition and the

input of a third control word CS/A, the memory is set ready to read. During acknowledge clock

no. 9, the memory information is transferred in parallel to the internal data register. Subsequent to

the falling edge of the acknowledge clock, the data output is low-impedance and the first data bit can

be sampled, see figure 4.

With each shift clock, an additional bit reaches the output. After reading a byte, the internal address

counter is automatically incremented through the master receiver acknowledge, so that any number

of memory locations can be read one after the other. At address 512, an overflow to address 0 is not

initiated. With the stop condition, the data output returns to high-impedance mode. The internal

sequence control of the memory component is reset from the read to the quiescent with the stop

condition.

Semiconductor Group

123 4 5 6 7...12

下载PDF

型号	品牌	描述	获取价格	数据表
Q67100-H5101	INFINEON	NONVOLATILE MEMORY 8-KBIT EPROM WITH IC BUS INTERFACE	获取价格
Q67100-H5139	INFINEON	PLL with I2C Bus for AM/FM Receivers	获取价格
Q67100-H5142	INFINEON	Picture-in-Picture Processor with On-Chip PLL	获取价格
Q67100-H5148	INFINEON	Quarter PIP Processor	获取价格
Q67100-H5156	INFINEON	Expanded Decoder for Program Delivery Control and Video Program System EPDC / VPS Decoder	获取价格
Q67100-H5164	INFINEON	VPS / PDC-plus Decoder	获取价格