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Q67100-H5092 PDF预览

Q67100-H5092

更新时间: 2024-11-08 23:06:07
品牌 Logo 应用领域
英飞凌 - INFINEON 存储可编程只读存储器
页数 文件大小 规格书
12页 276K
描述
Nonvolatile Memory 1-Kbit E2PROM

Q67100-H5092 数据手册

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Nonvolatile Memory 1-Kbit E2PROM  
SDA 2516-5  
Preliminary Data  
MOS IC  
Features  
Word-organized reprogrammable nonvolatile memory  
2
in n-channel floating-gate technology (E PROM)  
128 × 8-bit organization  
Supply voltage 5 V  
Serial 2-line bus for data input and output (I C Bus)  
2
Reprogramming mode, 10 ms erase/write cycle  
Reprogramming by means of on-chip control (without  
external control)  
P-DIP-8-1  
Check for end of programming process  
Data retention > 10 years  
4
More than 10 reprogramming cycles per address  
Compatible with SDA 2516. Exception:  
Conditions for total erase and current consumption I  
.
CC  
Type  
Ordering Code  
Package  
SDA 2516-5  
Q67100-H5092  
P-DIP-8-1  
Circuit Description  
2
I C Bus Interface  
2
The I C Bus is a bidirectional 2-line bus for the transfer of data between various integrated circuits.  
It consists of a serial data line SDA and a serial clock line SCL. The data line requires an external  
pull-up resistor to VCC (open drain output stage).  
2
The possible operational states of the I C Bus are shown in figure 1. In the quiescent state, both  
lines SDA and SCL are high, i.e. the output stage of the data line is disabled. As long a SCL remains  
"1", information changes on the data bus indicate the start or the end of data transfer between two  
components.  
The transition on SDA from "1" to "0" is a start condition, the transition from "0" to "1" a stop  
condition. During a data transfer the information on the data bus will only change while the clock line  
SCL is "0". The information on SDA is valid as long as SCL is "1".  
2
In conjunction with an I C Bus system, the memory component can operate as a receiver and as a  
transmitter (slave receiver or slave transmitter). Between a start and stop condition, information is  
always transmitted in byte-organized form. Between the trailing edge of the eighth clock pulse and  
Semiconductor Group  
5
07.94  

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