Datasheet > Q67006-A5198

Q67006-A5198

更新时间： 2024-09-14 22:44:11

品牌	Logo	应用领域
英飞凌 - INFINEON		解码器光电二极管
页数	文件大小	规格书
23页	474K
描述
Decoder for Program Delivery Control and Video Program System PDC / VPS Decoder

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数据手册

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Q67006-A5198 数据手册

Decoder for Program Delivery

Control and Video Program System

PDC / VPS Decoder

SDA 5648

SDA 5648X

CMOS IC

Features

● Single-chip receiver for PDC data, broadcast either

– in Broadcast Data Service Packet (BDSP) 8/30/2

according to CCIR teletext system B, or

– in dedicated line no. 16 of the vertical blanking interval

(VPS)

● Reception of Unified Date and Time (UDT) broadcast in

BDSP 8/30/1

● Low external components count

P-DIP-14-3

● On-chip data and sync slicer

● I²C-Bus interface for communication with external

microcontroller

● Selection of PDC/VPS operating mode software controlled

by I²C-Bus register

● Pin and software compatible to VPS Decoder SDA 5642

● Supply voltage: 5 V ± 10 %

● Video input signal level: 0.7 Vpp to 1.4 Vpp

● Technology: CMOS

● Package: P-DIP-14-3 and P-DSO-20-1

● Operating temperature range: 0 to 70 °C

P-DSO-20-1

Type

Ordering Code

Q67000-A5186

Q67006-A5198

Package

SDA 5648

SDA 5648X

P-DIP-14-3

P-DSO-20-1 Tape & Reel

Functional Description

The CMOS circuit SDA 5648 is intended for use in video cassette recorders to retrieve control data

of the PDC system from the data lines broadcast during the vertical blanking interval of a standard

video signal.

The SDA 5648 is devised to handle PDC data transported either in Broadcast Data Service Packet

(BDSP) 8/30 format 2 (bytes no. 13 through 25) of CCIR teletext system B or in the dedicated data

line no. 16 in the case of VPS.

Furthermore it is able to receive the Unified Date and Time (UDT) information transmitted in bytes

no. 15 through 21 of packet 8/30 format 1.

Semiconductor Group

12.94

12 3 4 5 6 7...23

中文翻译

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