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PM7382

更新时间： 2024-01-10 10:31:04

品牌	Logo	应用领域
PMC		/
页数	文件大小	规格书
2页	33K
描述
Frame Engine and Data Link Manager 32P256

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技术参数
数据手册

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PM7382 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
Reach Compliance Code：	unknown	HTS代码：	8542.31.00.01
风险等级：	5.91	JESD-30 代码：	S-PBGA-B329
端子数量：	329	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA329,23X23,50
封装形状：	SQUARE	封装形式：	GRID ARRAY
电源：	2.5,3.3 V	认证状态：	Not Qualified
子类别：	Serial IO/Communication Controllers	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	uPs/uCs/外围集成电路类型：	SERIAL IO/COMMUNICATION CONTROLLER, MULTI PROTOCOL
Base Number Matches：	1

PM7382 数据手册

PM7382

FREEDM-32P256

Frame Engine and Data Link Manager 32P256

• Supports up to 32 bi-directional HDLC

channels, each assigned to an

CRC-CCITT and CRC-32 frame-check

sequences.

• For each channel, the HDLC

transmitter supports programmable

flag-sequence generation, bit stuffing

and frame-check sequence

generation. The transmitter supports

the generation of both CRC-CCITT

and CRC-32 frame-check sequences.

The transmitter also aborts packets

under the direction of the host or

automatically when the channel

underflows.

• Provides 32 kbytes of on-chip memory

for partial packet buffering in both the

transmit and receive directions. You

can configure this memory to support a

variety of different channel

OVERVIEW

The FREEDM-32P256 chip offers the

following features:

unchannelized arbitrary-rate link,

subject to a maximum aggregate link

clock-rate of 64 MHz in each direction.

• Channels assigned to links 0 to 2

support clock rates up to 52 MHz.

Channels assigned to links 3 to 31

support clock rates up to 10 MHz. In

the special case where no more than 3

high-speed links are used, the

• Single-chip multi-channel HDLC

controller with a 66 MHz, 32-bit

Peripheral Component Interconnect

(PCI) 2.1 compatible bus for

configuration, monitoring, and transfer

of packet data.

• An on-chip DMA controller with

scatter/gather capabilities.

maximum aggregate link clock-rate is

156 MHz.

• Supports up to 256 bi-directional

HDLC channels assigned to a

maximum of 32 channelized T1/J1/E1

links. You can program the number of

time-slots assigned to an HDLC

channel from 1 to 24 (for T1/J1) and

from 1 to 31 (for E1).

• Supports up to 256 bi-directional

HDLC channels assigned to a

maximum of 32 MVIP digital telephony

buses at 2.048 Mbit/s per link, or

8 H-MVIP buses at 8.192 Mbit/s per

link.

• Links configured for channelized

T1/J1/E1 or unchannelized operation

support the gapped-clock method for

determining time-slots, which is

backwards compatible with the

FREEDM-8 and FREEDM-32 devices.

• For each channel, the HDLC receiver

supports programmable flag-sequence

detection, bit de-stuffing and

configurations: from a single channel

with 32 kbytes of buffering, to 256

channels, each with a minimum of 48

bytes of buffering.

• Provides a standard five signal

P1149.1 JTAG test-port for boundary

scan board-test purposes.

frame-check sequence validation. The

receiver supports the validation of both

BLOCK DIAGRAM

AD[31:0]

C/BEB[3:0]

PAR

RD[31:0]

RCLK[31:0]

RFPB[3:0]

RMVCK[3:0]

RMV8DC

RMV8FPC

RFP8B

Receive

DMA

Controller

(RMAC256)

FRAMEB

TRDYB

IRDYB

STOPB

DEVSELB

IDSEL

LOCKB

REQB

Receive

Receive HDLC

Processor/Partial

Packet Buffer

(RHDL256)

Channel

Assigner

(RCAS256)

PCI

Controller

(GPIC256)

Performance

Monitor (PMON)

GNTB

PERRB

SERRB

PCIINTB

PCICLK

PCICLKO

M66EN

TD[31:0]

Transmit

DMA

Controller

(TMAC256)

Transmit

Channel

Assigner

(TCAS256)

TCLK[31:0]

Transmit HDLC

Processor/ Partial

Packet Buffer

(THDL256)

TFPB[3:0]

TMVCK[3:0]

TMV8DC

TMV8FPC

TFP8B

JTAG Port

PMC-2011578 (r2)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

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与PM7382相关器件

型号	品牌	描述	获取价格	数据表
PM7382?	ETC	PMC-2010333 FREEDM-32P256 Data Sheet [2.45 MB]	获取价格
PM73-820K-RC	BOURNS	General Purpose Inductor, 82uH, 10%, 1 Element, Ferrite-Core, SMD, ROHS COMPLIANT	获取价格
PM7382-PGI	PMC	Multi Protocol Controller, CMOS, PBGA329,	获取价格
PM7382-PI	PMC	FRAME ENGINE AND DATA LINK MANAGER 32P256	获取价格
PM7383	PMC	FRAME ENGINE AND DATA LINK MANAGER 32A256	获取价格
PM7383?	ETC	Data Sheet Errata\|PMC-2010337 [159 kB]?	获取价格

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