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PM7389 PDF预览

PM7389

更新时间： 2024-02-20 05:03:24
品牌 Logo 应用领域
PMC /
页数 文件大小 规格书
2页 44K
描述
Frame Engine and Datalink Manager

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PM7389 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：BGA, BGA520,31X31,50Reach Compliance Code：compliant
风险等级：5.9JESD-30 代码：S-PBGA-B520
JESD-609代码：e0湿度敏感等级：3
端子数量：520最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA520,31X31,50
封装形状：SQUARE封装形式：GRID ARRAY
电源：1.8,3.3 V认证状态：Not Qualified
子类别：ATM/SONET/SDH ICs表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
Base Number Matches：1

PM7389 数据手册

 浏览型号PM7389的Datasheet PDF文件第2页 
PM7389  
FREEDM 84A1024  
Preliminary  
Frame Engine and Datalink Manager  
• Support for 3 egress fragmentation  
sizes (128, 256, and 512 bytes)  
configurable on a per multilink bundle.  
Optionally full packet transfers are  
supported on a per bundle basis.  
• Supports up to 42 multilink bundles  
with up to 12 member links per bundle.  
These bundles are composed of  
independent HDLC channels.  
• Support for up to 100ms of intra bundle  
skew in the receive direction when  
supporting the minimum fragment size.  
• Support for PPP header compression  
as per RFC 1661.  
• Link Control protocol packets are  
identified by the PID as control  
protocols and will be forwarded to the  
Any-PHY interface.  
FEATURES  
• Single-chip multi-channel packet  
processor supporting a maximum  
aggregate bandwidth of 156 Mbit/s for  
line rate throughput transfers of packet  
sizes from 40 to 9.6 Kbytes, for up to  
an aggregate of 84 T1s, 63 E1s, or 3  
DS-3s.  
• Provides simultaneous support of  
PPP, Frame Relay, Multilink-PPP and  
Multilink-Frame Relay protocols.  
Alternative protocols supported via  
HDLC termination and full packet store  
of the data within the HDLC structure.  
FRAME RELAY  
• Link layer address lookup can be  
performed based on HDLC channel  
and 10 bit DLCI for HDLC channels  
supporting Frame Relay protocols.  
• The lookup algorithm can support a  
maximum of 16 K connection  
identifiers (CIs) amongst multilink FR  
bundles. The connection identifiers  
are ignored in singlelink FR channels.  
• Control frames are identified and  
forwarded to Any-PHY interface.  
• 12 bit sequence numbers supported.  
• FECN, BECN, and DE ingress  
processing as per FRF.12.  
PPP  
MULTILINK PPP AND FRAME  
RELAY BUNDLES  
• Capable of supporting fragment sizes  
from 1 to 9.6 Kbytes.  
• Support for 16 COS levels in  
accordance with RFC 2686.  
• Either 12 bit or 24 bit sequence  
number, with short and long fragment  
header formats, is supported.  
BLOCK DIAGRAM  
TXCLK  
TXADDR[15:0]  
TPA  
TXDATA[15:0]  
TXPRTY  
TRDY  
TSX  
TEOP  
TMOD  
TERR  
DDLL-  
140  
JTAG  
Microprocessor I/F (BUMP2)  
Tx ANY-PHY  
I/F (TAPI-12)  
ACIFP  
CIFPOUT  
ADATA[7:0]  
ADP  
Egress  
Queue  
Tx  
Tx HDLC  
Fragment  
Builder  
(TFRAG)  
Manager  
(EQM-12)  
Transmit  
Channel  
Assigner  
(TCAS-12)  
Processor /  
Partial Packet  
Buffer  
Insert  
SBI  
(INSBI)  
CCDAT[35:0]  
CCADD[17:0]  
CCWEB  
APL  
AV5  
SRAM  
Controller  
(SRAMC)  
(THDL-12)  
AJUST_REQ  
AACTIVE  
ADETECT[1:0]  
CCSELB  
CCBSELB[1:0]  
Performance  
Monitor  
(PM-12)  
CBDAT[47:0]  
CBADD[12:0]  
CBWEB  
CBCSB  
CBRASB  
CB DRAM  
Controller  
(CB_DRAMC)  
REFCLK  
CBCASB  
CBBS[1:0]  
Rx HDLC  
Processor /  
Partial Packet  
Buffer  
DDATA[7:0]  
DDP  
RXCLK  
RXADDR[3:0]  
RPA  
Ingress  
Queue  
Manager  
(EQM-12)  
Rx  
Fragment  
Builder  
Receive  
Channel  
Assigner  
(RCAS-12)  
Frame  
Builder  
(FRMBLD)  
(RHDL-12)  
Extract  
SBI  
(EXSBI)  
(RFRAG)  
DPL  
RENB  
RXDATA[15:0]  
RXPRTY  
RVAL  
DV5  
Rx ANY-PHY  
I/F  
(RAPI-12)  
DC1FP  
RS DRAM  
Controller  
RSX  
RSOP  
(RS_DRAMC)  
REOP  
RMOD  
RERR  
Data  
Control  
PMC-1991477 (r2)  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
© Copyright PMC-Sierra, Inc. 2001  
12

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