Datasheet > PM7339

PM7339

更新时间： 2024-11-11 22:44:23

品牌	Logo	应用领域
PMC		/
页数	文件大小	规格书
2页	36K
描述
Quad Cell Delineation Block Device

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技术参数
数据手册

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PM7339 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	27 X 27 MM, 1.45 MM HEIGHT, SBGA-256	Reach Compliance Code：	unknown
风险等级：	5.92	应用程序：	ATM
JESD-30 代码：	S-PBGA-B256	JESD-609代码：	e0
长度：	27 mm	湿度敏感等级：	3
功能数量：	1	端子数量：	256
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装形状：	SQUARE	封装形式：	GRID ARRAY, LOW PROFILE
峰值回流温度（摄氏度）：	225	认证状态：	Not Qualified
座面最大高度：	1.58 mm	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
电信集成电路类型：	ATM/SONET/SDH NETWORK INTERFACE	温度等级：	INDUSTRIAL
端子面层：	TIN LEAD	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	30	宽度：	27 mm
Base Number Matches：	1

PM7339 数据手册

PM7339

PMC-Sierra,Inc.

S/UNI®-CDB

Quad Cell Delineation Block Device

framer/line interface chips for DS-1

and E1 applications.

(for use with PPP packets), and

FEATURES

• Quad cell delineation block operating

up to a maximum rate of 52 Mbit/s.

• Provides a UTOPIA Level 2-

accumulates the number of received

idle cells, the number of received cells

written to the FIFO and the number of

HCS errors.

• Provides a four cell FIFO for rate

decoupling between the line, and a

higher layer processing entity. FIFO

latency may be reduced by changing

the number of operational cell FIFOs.

• Provides programmable pseudo-

random test-sequence detection and

analysis features.

• Provides programmable pseudo-

random test pattern generation,

detection and analysis features.

• Provides performance monitoring

counters suitable for accumulation

periods of up to 1 second.

compatible ATM-PHY Interface.

• Implements the Physical Layer

Convergence Protocol (PLCP) for DS1

transmission systems according to the

ATM Forum User Network Interface

specification and ANSI TA-TSY-

000773, TA-TSY-000772, and E1

transmission systems according to the

ETSI 300-269 and ETSI 300-270.

• Supports SMDS PLCP and ATM Direct

Mapping into various rate transmission

systems in the following formats:

RECEIVER SECTION

• Provides PLCP frame synchronization,

path overhead extraction and cell

extraction for DS1 and E1 PLCP

formatted streams.

• Provides a 50 MHz 8-bit wide or 16-bit

wide UTOPIA FIFO buffer in the

receive path with parity support, and

multi-PHY (Level 2) control signals.

• Provides ATM framing using cell

delineation. ATM cell delineation may

optionally be disabled to allow all cell

bytes to pass regardless of cell

delineation status.

TRANSMITTER SECTION

• Provides a 50 MHz 8-bit wide or 16-bit

wide Utopia FIFO buffer in the transmit

path with parity support and multi-PHY

(Level 2) control signals.

• Provides optional ATM cell scrambling,

header scrambling (for use with PPP

packets), HCS generation/insertion,

programmable idle cell insertion,

•

E1 (2.048 Mbit/s) in CRC-4 and

PCM30;

•

T1 (1.544 Mbit/s) in ESF and SF;

Arbitrary Cell Rate (up to 52 Mbit/s)

with ATM Direct Mapping only.

• Uses the PMC-Sierra PM4341 T1XC,

PM4344 TQUAD, PM6341 E1XC, and

PM6344 EQUAD T1 and E1

diagnostics features and accumulates

transmitted cells read from the FIFO.

• Provides cell descrambling, header

check sequence (HCS) error detection,

idle cell filtering, header descrambling

BLOCK DIAGRAM

JTAG Test

Access

Port

DTCA[4:1]

TDAT[15:0]

TPRTY

TSOC

TCA

TADR[4:0]

SPLT

Transmit ATM

and

TDATO[4:1]

TOHM[4:1]

TCLK[4:1]

TXCP_50

Cell

TXFF

4 Cell

FIFO

PLCP Framer

TENB

TFCLK

PHY_ADR[2:0]

System

I/F

Processor

ATM8

RFCLK

RENB

RADR[4:0]

RCA

RXCP_50

Cell

RXFF

4 Cell

FIFO

ATM/SPLR

Receive ATM

and PLCP

Framer

RCLK[4:1]

RDATI[4:1]

ROHM[4:1]

Processor

RSOC

RPRTY

RDAT[15:0]

DRCA[4:1]

CPPM

PLCP/Cell Perf.

Monitor

Microprocessor

Interface

PMC-2000367 (R4)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

中文翻译

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