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PM7342 PDF预览

PM7342

更新时间: 2024-09-23 21:53:59
品牌 Logo 应用领域
PMC 复用器ATM集成电路SONET集成电路SDH集成电路电信电路异步传输模式
页数 文件大小 规格书
2页 49K
描述
32 Link Inverse Multiplexer for ATM (IMA) / UNI PHY

PM7342 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:BGA, BGA416,26X26,40Reach Compliance Code:compliant
风险等级:5.9JESD-30 代码:S-PBGA-B416
JESD-609代码:e0湿度敏感等级:3
端子数量:416最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA416,26X26,40
封装形状:SQUARE封装形式:GRID ARRAY
电源:1.8,3.3 V认证状态:Not Qualified
子类别:ATM/SONET/SDH ICs表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
Base Number Matches:1

PM7342 数据手册

 浏览型号PM7342的Datasheet PDF文件第2页 
PM7342  
S/UNI®-IMA-32  
Preliminary  
32 Link Inverse Multiplexer for ATM (IMA) / UNI PHY  
• Performs ICP and stuff-cell insertion  
and removal.  
• Supports IMA frame length (M) equal  
to 32, 64, 128, or 256.  
• Provides IMA layer statistic counts and  
alarms for support of IMA Performance  
and Failure Alarm Monitoring and MIB  
support.  
• Provides per link counters for statistics  
and performance monitoring.  
LINE INTERFACE  
FEATURES  
32 T1, E1, G.SHDSL or unchannelized  
links via 2-pin line interfaces.  
IMA  
• Supports up to 32 T1, E1, G.SHDSL or  
unchannelized links and up to 32 IMA  
groups with 1 to 32 links/group.  
• Link and Group State Machines  
implemented on-chip requiring no real  
time software in the data path.  
• Fully compliant with the ATM Forum  
Inverse Multiplexer for ATM (IMA)  
1.1 specification and backward  
compatible to IMA 1.0.  
• Supports both independent transmit  
clock (ITC) and common transmit clock  
(CTC) modes.  
• Supports all IMA Group Symmetry  
modes: Symmetric/Asymmetric  
configuration and operation.  
• Differential delay tolerance of 279 ms  
(for T1 links) and 226 ms (for E1 links).  
• Performs IMA differential delay  
calculation and synchronization.  
• Provides programmable limit on  
allowable differential delay and  
minimum number of links per group.  
Supports a 19.44 MHz Scalable Band-  
width Interconnect (SBI) bus interface for  
seamless interconnect to the PM8315  
TEMUX and PM8316 TEMUX-84.  
SBI supports two Synchronous  
Payload Envelopes (SPE). Each SPE  
can carry up to 16 T1s or 16 E1s.  
UNI  
UTOPIA / ANY-PHY INTERFACE  
• Each link is software configurable as  
either a UNI or part of an IMA group.  
• Performs receive cell Header Error  
Check (HEC) checking and transmit  
cell HEC generation.  
• Optionally supports receive cell  
payload unscrambling and transmit cell  
payload scrambling.  
• Supports 8- and 16-bit UTOPIA L2 and  
Any-PHY cell interfaces at clock rates  
up to 52 MHz.  
• Any-PHY transmit slave appears as a  
32 port multi-PHY. The PHY-ID of  
each cell is identified using in-band  
addressing.  
• Any-PHY receive slave appears as a  
single device. The PHY-ID of each cell  
is identified using in-band addressing.  
• UTOPIA L2 transmit and receive slave  
appears as a 31-port multi-PHY.  
• UTOPIA L2 receive slave can also  
appear as a single port with the logical  
port provided as a prepend.  
• Provides TC layer statistics counts and  
alarms for MIB support.  
ATM OVER FRACTIONAL T1/E1  
• Supports ATM over Fractional T1/E1  
compliant with the ATM Forum  
AF-PHY-0130.00 specification.  
BLOCK DIAGRAM  
SBI Add Bus I/F  
AC1FP  
ADATA[7:0]  
ADP  
Tx Slave  
ATM I/F  
MicroProcess I/F  
JTAG  
DLL  
Null  
Framer  
(SDFR32)  
APL  
AV5  
INSBI  
TCLK  
TPA  
TENB  
TADR[10:0]  
TCSB  
TSOP  
TSX  
TDAT[15:0]  
TPRTY  
AJUST_REQ  
AACTIVE  
ADETECT  
32-chan  
x 7 cell  
FIFO  
32-chan  
x
3 cell  
FIFO  
Any-PHY/  
UTOPIA  
Tx Slave  
(TXAPS)  
Tx IMA Processor  
TC Layer  
(TTTC32)  
(TIMA)  
32 Clk/Data  
(MCFD)  
TSCLK[31:0]  
TSDATA[31:0]  
CTSCLK  
TCAS  
IDCC  
Internal Bus  
Rx IMA  
Protocol  
Processor  
(RIPP)  
IDCC  
Rx Slave  
ATM I/F  
32 Clk/Data  
RSCLK[31:0]  
RCLK  
RCAS  
RSDATA[31:0]  
RPA  
Rx IMA  
Data Processor  
(RDAT)  
RENB  
32-chan  
x 2 cell  
FIFO  
31  
chan  
4 cell Rx Slave  
FIFO (RXAPS)  
Any-PHY/  
UTOPIA  
RADR[4:0]  
RCSB  
TC Layer  
(RTTC32)  
SBI Drop Bus I/F  
RSOP  
RSX  
DC1FP  
DDATA[7:0]  
DDP  
Cell Writer  
Cell Reader  
De-  
Framer  
RDAT[15:0]  
RPRTY  
EXSBI  
(SDDF32)  
DPL  
DV5  
Memory Interface  
(MEMI)  
PMC-2001523 (p5)  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
© Copyright PMC-Sierra, Inc. 2002  

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