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PM7342S/UNI-IMA-32 PDF预览

PM7342S/UNI-IMA-32

更新时间: 2024-09-24 15:48:07
品牌 Logo 应用领域
美高森美 - MICROSEMI /
页数 文件大小 规格书
2页 60K
描述
Telecom IC,

PM7342S/UNI-IMA-32 技术参数

生命周期:Obsolete包装说明:,
Reach Compliance Code:compliant风险等级:5.84
Is Samacsys:NBase Number Matches:1

PM7342S/UNI-IMA-32 数据手册

 浏览型号PM7342S/UNI-IMA-32的Datasheet PDF文件第2页 
PM7342  
S/UNI®-IMA-32  
Preliminary  
32 Link Inverse Multiplexer for ATM (IMA) / UNI PHY  
Provides programmable limit on  
allowable differential delay and  
minimum number of links per group.  
Performs ICP and stuff-cell insertion  
and removal.  
Supports IMA frame length (M) equal  
to 32, 64, 128, or 256.  
Provides IMA layer statistic counts and  
alarms for support of IMA Performance  
and Failure Alarm Monitoring and MIB  
support.  
ATM OVER FRACTIONAL T1/E1  
FEATURES  
Supports ATM over Fractional T1/E1  
compliant with the ATM Forum  
AF-PHY-0130.00 specification.  
IMA  
Supports up to 32 T1, E1, G.SHDSL or  
unchannelized links and up to 16 IMA  
groups with 1 to 32 links/group.  
Link and Group State Machines  
implemented on-chip requiring no real  
time software in the data path.  
Fully compliant with the ATM Forum  
Inverse Multiplexer for ATM (IMA)  
1.1 specification and backward  
compatible to IMA 1.0.  
Supports both independent transmit  
clock (ITC) and common transmit clock  
(CTC) modes.  
Supports all IMA Group Symmetry  
modes: Symmetric/Asymmetric  
configuration and operation.  
LINE INTERFACE  
32 T1, E1, G.SHDSL or unchannelized  
links via 2-pin line interfaces.  
UTOPIA / ANY-PHY INTERFACE  
Supports 8- and 16-bit UTOPIA L2 and  
Any-PHY cell interfaces at clock rates  
up to 52 MHz.  
Any-PHY transmit slave appears as a  
32 port multi-PHY. The PHY-ID of  
each cell is identified using in-band  
addressing.  
Any-PHY receive slave appears as a  
single device. The PHY-ID of each cell  
is identified using in-band addressing.  
UTOPIA L2 transmit and receive slave  
appears as a 31-port multi-PHY.  
UTOPIA L2 receive slave can also  
appear as a single port with the logical  
port provided as a prepend.  
Provides per link counters for statistics  
and performance monitoring.  
UNI  
Each link is software configurable as  
either a UNI or part of an IMA group.  
Performs receive cell Header Error  
Check (HEC) checking and transmit  
cell HEC generation.  
Optionally supports receive cell  
payload unscrambling and transmit cell  
payload scrambling.  
Differential delay tolerance of 279 ms  
(for T1 links) and 226 ms (for E1 links).  
Performs IMA differential delay  
calculation and synchronization.  
Provides TC layer statistics counts and  
alarms for MIB support.  
BLOCK DIAGRAM  
Tx Slave  
ATM I/F  
MicroProcess  
JTAG  
DLL  
I/F  
TCLK  
TPA  
TENB  
TADR[10:0]  
TCSB  
TSOP  
TSX  
Any-PHY/  
UTOPIA  
Tx Slave  
(TXAPS)  
TSCLK[31:0]  
TSDATA[31:0]  
32-chan  
x 7 cell FIFO  
(MCFD)  
32-chan x 3  
cell  
FIFO  
TC Layer  
(TTTC-32)  
Tx IMA Processor  
(TIMA)  
TCAS  
CTSCLK  
TDAT[15:0]  
TPRTY  
IDCC  
Internal Bus  
Rx IMA  
Protocol  
Processor  
(RIPP)  
IDCC  
Rx Slave  
ATM I/F  
RCLK  
RPA  
RENB  
RADR[4:0]  
RCSB  
RSOP  
RSX  
Rx IMA  
Data Processor  
(RDAT)  
31 chan  
4 cell  
FIFO  
Any-PHY/  
UTOPIA  
Rx Slave  
(RXAPS)  
RSCLK[31:0]  
32-chan  
x 2 cell  
FIFO  
TC Layer  
(RTTC-32)  
RCAS  
RSDATA[31:0]  
Cell Writer Cell Reader  
RDAT[15:0]  
RPRTY  
Memory Interface  
(MEMI)  
PMC-2001523 (p2)  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERSINTERNAL USE  
© Copyright PMC-Sierra, Inc. 2001  

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