Datasheet > PLL0930A

PLL0930A

更新时间： 2024-11-07 22:26:27

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
2页	77K
描述
PHASE LOCKED LOOP

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数据手册

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PLL0930A 数据手册

PLL0930A

9939 Via Pasar • San Diego, CA 92126

TEL (858) 621-2700 FAX (858) 621-2722

PHASE LOCKED LOOP

Rev A2

PHASE NOISE (1 Hz BW, typical)

FEATURES

900 960

MHz

• Frequency Range:

• Step Size:

100

KHz

•

- Style Package

PLL

APPLICATIONS

• Basestations

• Mobile Radios

Satellite Communications

•

VALUE

UNITS

PERFORMANCE SPECIFICATIONS

Frequency Range

900 - 960

MHz

RMS Phase Error (100 Hz - 100 KHz)

Harmonic Suppression (2nd, typ.)

Sideband Spurs (typ.)

0.75

-15

dBc

dBm

-65

Power Output

3±2

Load Impedance

Step Size

100

HIGH

KHz

Charge Pump Output Current

Switching Speed (typ., adjacent channel)

Startup Lock Time (typ.)

mSec

°C

-40 to +85

Operating Temperature Range

Package Style

PLL

POWER SUPPLY REQUIREMENTS

Supply Voltage (Vcc, nom.)

Supply Current (Icc, typ.)

Vdc

All specifications are typical unless otherwise noted and subject to change without notice.

APPLICATION NOTES

• AN-107 : How to Solder Z-COMM VCOs / PLLs

• AN-200 : Mounting and Grounding of Z-COMM PLLs

• AN-201 : PLL Fundamentals

AN-202 : PLL Functional Description

NOTES:

Reference Oscillator Signal: 5 MHz<f_osc<40 MHz

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