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PI90LV3810AE PDF预览

PI90LV3810AE

更新时间: 2024-11-16 19:59:55
品牌 Logo 应用领域
百利通 - PERICOM 光电二极管接口集成电路
页数 文件大小 规格书
11页 441K
描述
Line Receiver, 10 Func, 10 Rcvr, PDSO48, TSSOP-48

PI90LV3810AE 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP,针数:48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
输入特性:DIFFERENTIAL接口集成电路类型:LINE RECEIVER
接口标准:EIA-644; TIA-644JESD-30 代码:R-PDSO-G48
JESD-609代码:e3长度:12.5 mm
湿度敏感等级:1功能数量:10
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
认证状态:Not Qualified最大接收延迟:4 ns
接收器位数:10座面最大高度:1.2 mm
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:MATTE TIN (787)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:6.1 mmBase Number Matches:1

PI90LV3810AE 数据手册

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PI90LV3810/PI90LVR3810  
High-Speed Differential  
Line Receivers  
Features  
Description  
• Ten line receivers meet or exceed the requirements of the  
ThePI90LVx3810familyconsistsof tendifferentiallinereceivers  
with3-stateoutputsthatimplementLow-VoltageDifferentialSig-  
naling (LVDS). The PI90LVR3810 has integrated edge-triggered  
D-type flops. Any of the differential receivers will provide a valid  
logicaloutputstatewitha±100mVdifferentialinputvoltagewithin  
theinputcommon-modevoltagerangethatallows0to3Vofground  
potentialdifferencebetweentwoLVDSnodes.TheindependentEN  
pins can be used to place the outputs in either a normal logic state  
(high or low logic levels) or a high-impedance state. In high-  
impedance state, outputs neither load nor drive the bus lines.  
ANSITIA/EIA-644-1995Standard  
• Designed for signaling rates up to 660 Mbps  
• 0V to 3V common-mode input voltage range  
• Operates from a single 3.3V supply  
• Typical propagation delay time: 2.6ns  
• Output skew 100ps (typical)  
• Part-to-part skew is less than 1ns  
• PI90LVR3810  
The intended application of these devices, and their signaling  
techniques, is for point-to-point baseband data transmission over  
controlledimpedancemediaofapproximately100-Ohmswitha100-  
Ohm termination resistor. The transmission media may be printed  
circuit board traces, backplanes, or cables. The PI90LV3810’s 10  
receivers integrated into the same substrate allow precise timing  
alignment. In addition, the PI90LVR3810's integrated registers  
resynchronize the data to the system clock, for additional signal  
deskew.  
Set up time: typical 1ns  
Max. clock to output: 1ns  
• Integrated110-ohmterminationonPI90LVT386  
• LowVoltageTTL(LVTTL)levelsare5Vtolerant  
• Open-circuitfailsafe  
• Flow-through pin out  
• Packaging:  
48-Pin Thin Shrink Small Output TSSOP (A)  
TheintegratedregistersinthePI90LVR3810areparticularlysuitable  
forinterfacingwithLVDSdriverssuchasthePI90LV3811overlong  
distances where signal-to-signal skew may be a problem. On the  
positive transition of the differential clock (CLK±) input, the Q  
outputs of the flip-flop take on the logic levels set up at the  
differentialdata(RIN±)inputs.  
PI90LV3810  
Old data can be retained or new data can be entered while the  
outputs are in the high-impedance state. The EN pins do not affect  
the internal operation of the flip-flops.  
PI90LVR3810TruthTable  
SET  
R
OUT  
0
1
Q = D  
Q = 1  
PS8664  
02/21/03  
1

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